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MC56F8346/D Rev. 3.0, 10/2003
56F8346
Preliminary Technical Data
56F8346 16-bit Hybrid Controller
* Up to 60 MIPS at 60MHz core frequency * DSP and MCU functionality in a unified, C-efficient architecture * Access up to 1MB of off-chip program and data memory * Chip Select Logic for glueless interface to ROM and SRAM * 128KB of Program Flash * 4KB of Program RAM * 8KB of Data Flash * 8KB of Data RAM * 8KB of Boot Flash * Two 6-channel PWM Modules * Four 4-channel, 12-bit ADCs
RSTO EMI_MODE EXTBOOT 5 VPP 2
* * * * * * * * *
Temperature Sensor Two Quadrature Decoders Optional On-Chip Regulator FlexCAN Module Two Serial Communication Interfaces (SCIs) Up to two Serial Peripheral Interfaces (SPIs) Up to four General Purpose Quad Timers Computer Operating Properly (COP) / Watchdog JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, real-time debugging * Up to 62 GPIO lines * 144-pin LQFP Package
VCAP* 4
OCR_DIS VDD VSS 7 5 Digital Reg
VDDA 2
VSSA
RESET
6 3 3 6 3 4 4 4 5 4 4
* Configuration shown for on-chip 2.5V regulator
PWM Outputs Current Sense Inputs or GPIOC Fault Inputs PWM Outputs Current Sense Inputs or GPIOD Fault Inputs A/D0 ADCA A/D1 VREF A/D0 A/D1
PWMA
JTAG/ EOnCE Port
Analog Reg
16-Bit 56800E Core
Low Voltage Supervisor
Bit Manipulation Unit
PWMB
Program Controller and Hardware Looping Unit
Address Generation Unit
Data ALU 16 x 16 + 36 AE 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators
PAB PDB CDBR CDBW R/W Control XDB2 XAB1 XAB2 PAB PDB CDBR CDBW
6 External Address Bus Switch 2 8
Memory
ADCB Program Memory 64K x 16 Flash 2K x 16 RAM 4K x 16 Boot Flash Data Memory 4K x 16 Flash 4K x 16 RAM
A0-5 or GPIOA8-13 A6-7 or GPIOE2-3 A8-15 or GPIOA0-7 GPIOB0 or A16 D0-6 or GPIOF9-15 D7-15 or GPIOF0-8 WR RD GPIOD0-1 or CS2-3 PS (CS0) or GPIOD8 DS (CS1) or GPIOD9
4
4
2 2
Temp_Sense Quadrature Decoder 0 or Quad Timer A or GPIOC Quadrature Decoder 1 or Quad Timer B or SPI1 or GPIOC Quad Timer C or GPIOE Quad Timer D or GPIOE FlexCAN
System Bus Control
External Bus Interface Unit
7 External Data Bus Switch 9
Bus Control
2
IPBus Bridge (IPBB)
Decoding Peripherals
Clock resets PLL
Peripheral Device Selects
RW Control
IPAB
IPWDB
IPRDB
SPI0 or GPIOE
4
SCI1 or GPIOD
2
SCI0 or GPIOE
2
COP/ Interrupt Watchdog Controller
System O Integration R Module CLKO
P
O Clock Generator S C
XTAL EXTAL
IRQA IRQB
CLKMODE
56F8346 Block Diagram
(c) Motorola, Inc., 2003. All rights reserved.
56F8346 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . 3
1.1. 56F8346 Features. . . . . . . . . . . . . . . . . . . 1.2. 56F8346 Description . . . . . . . . . . . . . . . . 1.3. Award-Winning Development Environment . . . . . . . . . . . . . . . 1.4. Architecture Block Diagram . . . . . . . . . . 1.5. Product Documentation . . . . . . . . . . . . . 1.6. Data Sheet Conventions. . . . . . . . . . . . . . 3 4 5 5 8 9
Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . 113 8.2. Configuration . . . . . . . . . . . . . . . . . . . . 113 8.3. Memory Maps. . . . . . . . . . . . . . . . . . . 117
Part 9: Joint Test Action Group (JTAG) . . . . . . . . . . . . . . . . . . . . . 117
9.1. 56F8346 Information . . . . . . . . . . . . . . 117
Part 2: Signal/Connection Descriptions . 10
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 10 2.2. 56F8346 Signal Pins . . . . . . . . . . . . . . . 12
Part 10: Specifications . . . . . . . . . . . . . . 118
10.1. General Characteristics. . . . . . . . . . . 118 10.2. DC Electrical Characteristics . . . . . . . 123 10.3. AC Electrical Characteristics . . . . . . . 126 10.4. Flash Memory Characteristics . . . . . 127 10.5. External Clock Operation Timing . . . 128 10.6. Phase Locked Loop Timing . . . . . . . . 128 10.7. Crystal Oscillator Timing . . . . . . . . . 129 10.8. External Memory Interface Timing . . 129 10.9. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . 132 10.10. Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . 134 10.11. Quad Timer Timing . . . . . . . . . . . . . 137 10.12. Quadrature Decoder Timing . . . . . . 137 10.13. Serial Communication Interface (SCI) Timing . . . . . . . . . . . . . . . . . . 138 10.14. Controller Area Network (CAN) Timing . . . . . . . . . . . . 139 10.15. JTAG Timing . . . . . . . . . . . . . . . . . 139 10.16. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . . . 141 10.17. Equivalent Circuit for ADC Inputs. 142 10.18. Power Consumption . . . . . . . . . . . . 142
Part 3: On-Chip Clock Synthesis (OCCS) 30
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 30 3.2. External Clock Operation . . . . . . . . . . . 30 3.3. Registers. . . . . . . . . . . . . . . . . . . . . . . . . 32
Part 4: Memory Map . . . . . . . . . . . . . . . . 33
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 4.2. Program Map . . . . . . . . . . . . . . . . . . . . . 4.3. Interrupt Vector Table . . . . . . . . . . . . . . 4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . 4.5. Flash Memory Map . . . . . . . . . . . . . . . . 4.6. EOnCE Memory Map . . . . . . . . . . . . . . 4.7. Peripheral Memory Mapped Registers . 5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . 5.3. Functional Description. . . . . . . . . . . . . . 5.4. Block Diagram . . . . . . . . . . . . . . . . . . . 5.5. Operating Modes . . . . . . . . . . . . . . . . . . 5.6. Register Descriptions . . . . . . . . . . . . . . 5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 35 38 38 40 41 66 66 66 68 68 68 93
Part 5: Interrupt Controller (ITCN) . . . 66
Part 6: System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . 94
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . 94 6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3. Operating Modes . . . . . . . . . . . . . . . . . . 95 6.4. Operation Mode Register. . . . . . . . . . . . 95 6.5. Register Descriptions . . . . . . . . . . . . . . . 96 6.6. Clock Generation Overview . . . . . . . . 108 6.7. Power-Down Modes Overview . . . . . 108 6.8. Stop and Wait Mode Disable Function 109 6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Part 11: Packaging. . . . . . . . . . . . . . . . . 144
11.1. Package and Pin-Out Information 56F8346 . . . . . . 144
Part 12: Design Considerations . . . . . . . 148
12.1. Thermal Design Considerations . . . . 148 12.2. Electrical Design Considerations . . . 149 12.3. Power Distribution and I/O Ring Implementation . . . . . . . . . . . 150
Part 13: Ordering Information . . . . . . . 151
Part 7: Security Features . . . . . . . . . . . 110
7.1. Operation with Security Enabled 110 7.2. Flash Access Blocking Mechanisms . . 110 Please see http://www.motorola.com/semiconductors for the most current Data Sheet revision. 2 56F8346 Technical Data Preliminary MOTOROLA
56F8346 Features
Part 1 Overview
1.1 56F8346 Features
1.1.1
* * * * * * * * * * * * * *
Digital Signal Processing Core
Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture As many as 60 Million Instructions Per Second (MIPS) at 60 MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators including extension bits Arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/EOnCE debug programming interface
1.1.2
* * *
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security protection feature On-chip memory including a low-cost, high-volume Flash solution -- 128KB of Program Flash -- 4KB of Program RAM -- 8KB of Data Flash -- 8KB of Data RAM -- 8KB of Boot Flash
*
Off-chip memory expansion capabilities programmable for 0 - 30 wait states -- Access up to 1MB of program memory or 1MB of data memory -- Chip select logic for glue-less interface to ROM and SRAM Temperature Sense diode can be connected, on the board, to any of the ADC inputs to monitor the on-chip temperature EEPROM emulation capability
* *
1.1.3
*
Peripheral Circuits for 56F8346
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and three Fault inputs, fault-tolerant design with dead time insertion, supports both center-aligned and edge-aligned modes Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, channels 2 and 3
56F8346 Technical Data Preliminary 3
*
MOTOROLA
* * * * * * * * * * * * * * *
Temperature Sensor, which can be tied to an analog input pin to monitor the on-chip temperature Two four-input Quadrature Decoders or two additional Quad Timers Four dedicated General Purpose Quad Timers totaling three dedicated pins: Timer C with one pin and Timer D with two pins Optional On-Chip Regulator FlexCAN (CAN Version 2.0 B-compliant ) Module with 2-pin port for transmit and receive Two Serial Communication Interfaces each with two pins (or four additional GPIO lines) Up to two Serial Peripheral Interfaces (SPIs) with configurable 4-pin port (or eight additional GPIO lines). SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B Computer-Operating Properly (COP) / Watchdog timer Two dedicated external interrupt pins 62 General Purpose I/O (GPIO) pins External reset input pin for hardware reset External reset output pin for system reset Integrated low-voltage interrupt module JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent, real-time debugging Software-programmable, Phase Lock Loop-based frequency synthesizer for the core clock
1.1.4
* * * * * *
Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available ADC smart power management Each peripheral can be individually disabled to save power
1.2 56F8346 Description
The 56F8346 is a member of the 56800E core-based family of hybrid controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8346 is well-suited for many applications. The 56F8346 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, industrial control for power, lighting, and automation. The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications. The 56F8346 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8346 also provides two external dedicated interrupt lines and up to 62 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
4
56F8346 Technical Data Preliminary
MOTOROLA
Award-Winning Development Environment
The 56F8346 hybrid controller includes 128KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F8346 is the inclusion of two Pulse Width Modulator (PWM) modules. These modules each incorporate three complementary, individually programmable PWM signal output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM outputs) to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A "smoke-inhibit", write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM modules provide reference outputs to synchronize the analog-to-digital converters through two channels of Quad Timer C. The 56F8346 incorporates two Quadrature Decoders capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a timeout value to alert when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This hybrid controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCIs), two Serial Peripheral Interfaces (SPIs), and four Quad Timers. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIOs) if that function is not required. A Flex Controller Area Network interface (CAN Version 2.0 A/B compliant) and an internal interrupt controller are included on the 56F8346.
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
The 56F8346 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories, the external memory interface and the IP Bus Bridge. Table 1-1 lists the internal buses in the 56800E architecture and provides a brief description of their function. Figure 1-2 shows the peripherals and control blocks connected to the IP Bus Bridge. The figures do not show the on-board regulator and power and ground signals. They also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection Descriptions, to see which signals are multiplexed with those of other peripherals.
MOTOROLA 56F8346 Technical Data Preliminary 5
Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions. In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer C input channel as indicated. The timer can then be used to introduce a controllable delay before generating its output signal. The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals.
5
JTAG / EOnCE Boot Flash
pdb_m[15:0] pab[20:0]
Program Flash Program RAM
cdbw[31:0]
56800E
CHIP TAP Controller
17
Address Data Control
EMI
16 6
TAP Linking Module
xab1[23:0] xab2[23:0]
Data RAM Data Flash
External JTAG Port cdbr_m[31:0] xdb2_m[15:0]
IP Bus Bridge
To Flash
Control Logic
Flash Interface Units IP Bus
Figure 1-1 System Bus Interfaces
Note: Flash memories are encapsulated within the Flash Interface Unit (FIU). Flash control is accomplished by the I/O to the FIU over the peripheral bus, while reads and writes are completed between the core and the Flash memories. The primary data RAM port is 32 bits wide. Other data ports are16 bits.
Note:
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56F8346 Technical Data Preliminary
MOTOROLA
Architecture Block Diagram
To/From IP Bus Bridge
CLKGEN (OSC/PLL)
Interrupt Controller Low Voltage Interrupt
Timer A
POR & LVI
4 2
Quadrature Decoder 0 Timer D
System POR
SIM
RESET
COP Reset Timer B 4 COP FlexCAN 2
Quadrature Decoder 1 SPI 1
PWMA
12 SYNC Output 13
GPIOA GPIOB GPIOC GPIOD
PWMB SYNC Output ch3i Timer C ch3o
ch2i ch2o
1
GPIOE GPIOF 4 2 2 SPI0 SCI0 Temp. Sense SCI1
Note: ADCA and ADCB use the same voltage reference circuit with VREFH, VREFP, VREFMID, VREFN, and VREFLO pins.
8 ADCB ADCA 1 8
IP Bus
Figure 1-2 Peripheral Subsystem
MOTOROLA 56F8346 Technical Data Preliminary 7
Table 1-1 Bus Signal Names
Name
pdb_m[15:0] cdbw[15:0] pab[20:0]
Function Program Memory Interface
Program data bus for instruction word fetches or read operations. Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus. cdbw[31:0] xab1[23:0] Primary core data bus for memory writes. Addressed via xab1 bus. Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written on cdbw and returned on cdbr_m. Also used to access memory mapped I/O.
Secondary Data Memory Interface
xdb2_m[15:0] Secondary data bus used for Secondary data address bus xab2 in the dual memory reads. xab2[23:0] Secondary data address bus used for the second of two simultaneous accesses. Capable of addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0] Peripheral Bus accesses all On-Chip peripherals registers. This bus operates at the same clock rate as the Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m.
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.
1.5 Product Documentation
The four documents in Table 1-2 are required for a complete description and proper design with the 56F8346. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at http://www.motorola.com/semiconductors.
Table 1-2 56F8346 Chip Documentation
Topic DSP56800E Reference Manual Description Detailed description of the 56800E family architecture, and 16-bit hybrid controller core processor and the instruction set Detailed description of peripherals of the 56F8300 devices Electrical and timing specifications, pin descriptions, and package descriptions (this document) Summary description and block diagram of the 56F8346 core, memory, peripherals and interfaces Details any chip issues that might be present Order Number DSP56800ERM/D
568300 Peripheral User Manual 56F8346 Technical Data Sheet 56F8346 Product Brief 56F8346 Errata
MC56F8300UM/D
MC56F8346/D
MC56F8346PB/D
MC56F8346E/D
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56F8346 Technical Data Preliminary
MOTOROLA
Data Sheet Conventions
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL
"asserted" "deasserted" Examples:
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
MOTOROLA
56F8346 Technical Data Preliminary
9
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8346 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group Power (VDD or VDDA)1 Power Option Control Ground (VSS or VSSA) Supply Capacitors & VPP PLL and Clock Address Bus Data Bus Bus Control Interrupt and Program Control Pulse Width Modulator (PWM) Ports Serial Peripheral Interface (SPI) Port 0 Quadrature Decoder Port 02 Quadrature Decoder Port 13 Serial Communications Interface (SCI) Ports CAN Ports Analog to Digital Converter (ADC) Ports Timer Module Ports JTAG/Enhanced On-Chip Emulation (EOnCE) Temperature Sense Number of Pins 9 1 6 6 4 17 16 6 6 25 4 4 4 4 2 21 3 5 1
1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs 2. Alternately, can function as Quad Timer pins or GPIO 3. Pins in this section can function as Quad Timer, SPI #1, or GPIO
10
56F8346 Technical Data Preliminary
MOTOROLA
Introduction
Power Power Power Ground Ground
VDD_IO VDDA_ADC VDDA_OSC_PLL VSS VSSA_ADC OCR_DIS
7 1 1 5 1 1 1 1 1 1 PHASEA0 (TA0, GPIOC4) PHASEB0 (TA1, GPIOC5) INDEX0 (TA2, GPIOC6) HOME0 (TA3, GPIOC7) Quadrature Decoder 0 or Quad Timer A or GPIO
Other Supply Ports
VCAP1 - VCAP4 VPP1 & VPP2 CLKMODE EXTAL XTAL CLKO A0 - A5 (GPIOA8 - 13)
56F8346
4 2 1 1 1 1 6 2 8 1
1 1 1 1 1 1 1 1
SCLK0 (GPIOE4) MOSI0 (GPIOE5) MISO0 (GPIOE6) SS0 (GPIOE7) PHASEA1(TB0, SCLK1, GPIOC0) PHASEB1 (TB1, MOSI1, GPIOC1) INDEX1 (TB2, MISO1, GPIOC2) HOME1 (TB3, SS1, GPIOC3)
SPI0 or GPIO
PLL and Clock
Quadrature Decoder 1 or Quad Timer B or SPI 1 or GPIO
External Address Bus or GPIO
A6 - A7 (GPIOE2 - 3) A8 - A15 (GPIOA0 - 7) GPIOB0 (A16)
6 3 3
PWMA0 - 5 ISA0 - 2 (GPIOC8 - 10) FAULTA0 - 2
PWMA or GPIO
External Data Bus or GPIO
D0-D6 (GPIOF9 - 15) D7 - D15 (GPIOF0 - 8)
7 9 6 3 4
PWMB0 - 5 ISB0 - 2 (GPIOD10 - 12) FAULTB0 - 3
PWMB or GPIO
RD External Bus Control or GPIO WR PS (CS0)(GPIOD8) DS (CS1)(GPIOD9) GPIOD0 - 1 (CS2 - 3)
1 1 1 1 2
8 5 8 1
ANA0 - 7 VREF ANB0 - 7 Temp_Sense
ADCA ADCB Temp Sense
1 SCI 0 or GPIO SCI 1 or GPIO TXD0 (GPIOE0) RXD0 (GPIOE1) TXD1 (GPIOD6) RXD1 (GPIOD7) TCK TMS TDI TDO TRST 1 1 1 1 1 1 1 1 1 1 1 2
CAN_RX CAN_TX
FlexCAN QUAD TIMERS C or GPIO QUAD TIMERS D or GPIO
TC0 (GPIOE8) TD0 - 1 (GPIOE10 - 11)
JTAG/ EOnCE Port
1 1 1 1 1 1
IRQA IRQB EXTBOOT EMI_MODE RESET RSTO INTERRUPT/ PROGRAM CONTROL
Figure 2-1 56F8346 Signals Identified by Functional Group1 (144 pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
MOTOROLA
56F8346 Technical Data Preliminary
11
2.2 56F8346 Signal Pins
After reset, all pins are by default the primary function. Any alternate functionality must be programmed.
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Signal Description
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDDA_ADC
1 16 31 38 66 84 119 102
Supply
I/O Power -- This pin supplies 3.3V power to the chip I/O interface.
Supply
ADC Power -- This pin supplies 3.3V power to the ADC modules. It must be connected to a clean analog power supply. Oscillator and PLL Power -- This pin supplies 3.3V power to the OSC and to the internal regulator that in turn supplies the phase locked loop. It must be connected to a clean analog power supply. VSS -- These pins provide ground for chip logic and I/O drivers.
VDDA_OSC_PLL
80
Supply
VSS VSS VSS VSS VSS VSSA_ADC
27 37 63 69 144 103
Supply
Supply
ADC Analog Ground -- This pin supplies an analog ground to the ADC modules. Input On-Chip Regulator Disable -- Tie this pin to VSS to enable the on-chip regulator Tie this pin to VDD to disable the on-chip regulator This pin is intended to be a static DC signal from power-up to shut down. Do not try to toggle this pin for power savings during operation.
OCR_DIS
79
Input
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56F8346 Technical Data Preliminary
MOTOROLA
56F8346 Signal Pins
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Supply Signal Description
VCAP1 VCAP2 VCAP3 VCAP4 VPP1 VPP2 CLKMODE
51 128 83 15 125 2 87
Supply
VCAP1 - 4 -- When OCR_DIS is tied to VSS (regulator enabled), connect each pin to a 2.2F or greater bypass capacitor in order to bypass the core logic voltage regulator, required for proper chip operation. When OCR_DIS is tied to VDD (regulator disabled), these pins become VDD_CORE and should be connected to a regulated 2.5V power supply. VPP1 - VPP2 -- These pins should be left unconnected as an open circuit for normal functionality.
Input
Input
Input
Input
Clock Input Mode Selection -- This input determines the function of the XTAL and EXTAL pins. 1 = External clock input on XTAL is used to directly drive the input clock of the chip. The EXTAL pin should be grounded. 0 = A crystal or ceramic resonator should be connected between XTAL and EXTAL.
EXTAL
82
Input
Input
External Crystal Oscillator Input -- This input can be connected to an 8MHz external crystal. Tie this pin low if XTAL is driven by an external clock source. Crystal Oscillator Output -- This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to GND. The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL.
XTAL
81
Input/ Output
Chip-driven
CLKO
3
Output
Tri-Stated
Clock Output -- This pin outputs a buffered clock signal. Using the SIM CLKO Select Register (SIM_CLKOSR), this pin can be programmed as any of the following: disabled, CLK_MSTR (system clock), IP Bus clock, oscillator output, prescaler clock and postscaler clock. Other signals are also available for test purposes. See Section 6.5.7 for details.
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Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Tri-stated Signal Description
A0
138
Output
(GPIOA8) A1 (GPIOA9) A2 (GPIOA10) A3 (GPIOA11) A4 (GPIOA12) A5 (GPIOA13) A6 10
Address Bus -- A0 - A5 specify six of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A0-A16 and EMI control signals are tri-stated when the external bus is inactive. Port A GPIO -- These six GPIO pins can be individually programmed as input or output pins. After reset, these pins default to address bus functionality and must be programmed as GPIO. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOA_PUR register. Example: GPIOA8, clear bit 8 in the GPIOA_PUR register.
11
12
13
14
17
Output
Tri-stated
(GPIOE2) A7 (GPIOE3) 18
Schmitt Input/ Output
Input
Address Bus -- A6 - A7 specify two of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A0-A16 and EMI control signals are tri-stated when the external bus is inactive. Port E GPIO -- These two GPIO pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOE_PUR register. Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.
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56F8346 Signal Pins
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Tri-stated Signal Description
A8 (GPIOA0) A9 (GPIOA1) A10 (GPIOA2) A11 (GPIOA3) A12 (GPIOA4) A13 (GPIOA5) A14 (GPIOA6) A15 (GPIOA7) GPIOB0
19
Output
20
Schmitt Input/ Output
Input
Address Bus-- A8 - A15 specify eight of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A0-A16 and EMI control signals are tri-stated when the external bus is inactive. Port A GPIO -- These eight GPIO pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOA_PUR register. Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
21
22
23
24
25
26
33
Schmitt Input/ Output Output
Input
Port B GPIO -- This GPIO pin can be programmed as an input or output pin.
(A16)
Tri-stated
Address Bus -- A16 specifies one of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A0-A16 and EMI control signals are tri-stated when the external bus is inactive. After reset, the startup state of GPIOB0 (GPIO or address) is determined as a function of EXTBOOT, EMI_MODE and the Flash security setting. See Table 4-4 for further information on when this pin is configured as an address pin at reset. In all cases, this state may be changed by writing to GPIOB_PER. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOB_PUR register.
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Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Tri-stated Signal Description
D0 (GPIOF9) D1 (GPIOF10) D2 (GPIOF11) D3 (GPIOF12) D4 (GPIOF13) D5 (GPIOF14) D6 (GPIOF15) D7 (GPIOF0) D8 (GPIOF1) D9 (GPIOF2) D10 (GPIOF3) D11 (GPIOF4) D12 (GPIOF5) D13 (GPIOF6) D14 (GPIOF7)
59
Input/ Output
60
Data Bus -- D0 - D6 specify part of the data for external program or data memory accesses. Depending upon the state of the DRV bit in the SEMI bus control register (BCR), D0-D6 are tri-stated when the external bus is inactive. Port F GPIO -- These four GPIO pins can be individually programmed as input or output pins. At reset, these pins default to the EMI Data bus function. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOF_PUR register. Example: GPIOF9, clear bit 9 in the GPIOF_PUR register.
72
75
76
77
78
28
Input/ Output
Tri-stated
Data Bus -- D7 - D14 specify part of the data for external program or data memory accesses. Port F GPIO -- These eight GPIO pins can be individually programmed as input or output pins.
29 Input/ Output Input
30
At reset, these pins default to data bus functionality. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOF_PUR register. Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
32
133
134
135
136
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56F8346 Technical Data Preliminary
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56F8346 Signal Pins
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Tri-stated Signal Description
D15 (GPIOF8)
137
Input/ Output
Data Bus -- D15 specifies part of the data for external program or data memory accesses. Port F GPIO -- This GPIO pin can be individually programmed as an input or output pin. At reset, this pin defaults to the D15 function. To deactivate the internal pull-up resistor, clear bit 8 in the GPIOF_PUR register.
RD
45
Output
Tri-stated
Read Enable -- RD is asserted during external memory read cycles. When RD is asserted low, pins D0 - D15 become inputs and an external device is enabled onto the data bus. When RD is deasserted high, the external data is latched inside the device. When RD is asserted, it qualifies the A0 - A16, PS, DS, and CSn pins. RD can be connected directly to the OE pin of a Static RAM or ROM. Depending upon the state of the DRV bit in the SEMI bus control register (BCR), RD is tri-stated when the external bus is inactive. To deactivate the internal pull-up resistor, set the CTRL bit in the SIM_PUDR register.
WR
44
Output
Tri-stated
Write Enable -- WR is asserted during external memory write cycles. When WR is asserted low, pins D0 - D15 become outputs and the device puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0 - A16, PS, DS, and CSn pins. WR can be connected directly to the WE pin of a static RAM. Depending upon the state of the DRV bit in the SEMI bus control register (BCR), WR is tri-stated when the external bus is inactive. To deactivate the internal pull-up resistor, set the CTRL bit in the SIM_PUDR register.
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Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Tri-stated Signal Description
PS (CS0)
46
Output
(GPIOD8)
Program Memory Select -- This signal is actually CS0 in the EMI, which is programmed at reset for compatibility with the 56F80x PS signal. PS is asserted low for external program memory access. Depending upon the state of the DRV bit in the SEMI bus control register (BCR), PS is tri-stated when the external bus is inactive. Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. CS0 resets to provide the PS function as defined on the 56F80x devices. To deactivate the internal pull-up resistor, clear bit 8 in the GPIOD_PUR register.
DS (CS1)
47
Output
Tri-stated
(GPIOD9)
Data Memory Select -- This signal is actually CS1 in the EMI, which is programmed at reset for compatibility with the 56F80x DS signal. DS is asserted low for external data memory access. Depending upon the state of the DRV bit in the SEMI bus control register (BCR), DS is tri-stated when the external bus is inactive. Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. To deactivate the internal pull-up resistor, clear bit 9 in the GPIOD_PUR register.
GPIOD0 (CS2)
48
Input/ Output Output
Input
Port D GPIO -- These two GPIO pins can be individually programmed as input or output pins. Chip Select -- CS2 - CS3 may be programmed within the EMI module to act as chip selects for specific areas of the external memory map. Depending upon the state of the DRV bit in the SEMI bus control register (BCR), CS2 - CS3 is tri-stated when the external bus is inactive. At reset, these pins are configured as GPIO. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOD_PUR register. Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.
GPIOD1 (CS3)
49
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56F8346 Signal Pins
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Input Input Signal Description
TXD0 (GPIOE0)
4
Output Input/ Output
Transmit Data -- SCI0 transmit data output Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOE_PUR register.
RXD0 (GPIOE1)
5
Input Input/ Output
Input Input
Receive Data -- SCI0 receive data input Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOE_PUR register.
TXD1 (GPIOD6)
42
Output Input/ Output
Input Input
Transmit Data -- SCI1 transmit data output Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 6 in the GPIOD_PUR register.
RXD1 (GPIOD7)
43
Input Input/ Output
Input Input
Receive Data -- SCI1 receive data input Port D GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI input. To deactivate the internal pull-up resistor, clear bit 7 in the GPIOD_PUR register.
TCK
121
Schmitt Input
Input, pulled low internally
Test Clock Input -- This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-down resistor. Test Mode Select Input -- This input pin is used to sequence the JTAG TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register.
TMS
122
Schmitt Input
Input, pulled high internally
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Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Input, pulled high internally Signal Description
TDI
123
Schmitt Input
Test Data Input -- This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register.
TDO
124
Output
Tri-stated
Test Data Output -- This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. Test Reset -- As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware device reset is required and the EOnCE/JTAG module must not be reset. In this case, assert RESET, but do not assert TRST. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register.
TRST
120
Schmitt Input
Input, pulled high internally
PHASEA0
139
Schmitt Input Schmitt Input/ Output Schmitt Input/ Output
Input
Phase A -- Quadrature Decoder 0 PHASEA input
(TA0)
Input
TA0 -- Timer A Channel 0
(GPIOC4)
Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PHASEA0. To deactivate the internal pull-up resistor, clear bit 4 of the GPIOC_PUR register.
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56F8346 Signal Pins
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Input Signal Description
PHASEB0
140
Schmitt Input Schmitt Input/ Output Schmitt Input/ Output
Phase B -- Quadrature Decoder 0 PHASEB input
(TA1)
Input
TA1 -- Timer A Channel
(GPIOC5)
Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PHASEB0. To deactivate the internal pull-up resistor, clear bit 5 of the GPIOC_PUR register.
INDEX0
141
Schmitt Input Schmitt Input/ Output Schmitt Input/ Output
Input
Index -- Quadrature Decoder 0 INDEX input
(TA2)
Input
TA2 -- Timer A Channel 2
(GPOPC6)
Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is INDEX0. To deactivate the internal pull-up resistor, clear bit 6 of the GPIOC_PUR register.
HOME0
142
Schmitt Input Schmitt Input/ Output Schmitt Input/ Output
Input
Home -- Quadrature Decoder 0 HOME input
(TA3)
Input
TA3 -- Timer A Channel 3
(GPIOC7)
Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is HOME0. To deactivate the internal pull-up resistor, clear bit 7 of the GPIOC_PUR register.
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Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Input Signal Description
SCLK0
130
Schmitt Input/ Output Schmitt Input/ Output
SPI 0 Serial Clock -- In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCLK0. To deactivate the internal pull-up resistor, clear bit 4 in the GPIOE_PUR register.
(GPIOE4)
Input
MOSI0
132
Input/ Output
Input
SPI 0 Master Out/Slave In -- This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is MOSI0. To deactivate the internal pull-up resistor, clear bit 5 in the GPIOE_PUR register.
(GPIOE5)
Input/ Output
Input
MISO0
131
Input/ Output
Input
(GPIOE6) Input/ Output Input
SPI 0 Master In/Slave Out -- This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. Port E GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is MISO0. To deactivate the internal pull-up resistor, clear bit 6 in the GPIOE_PUR register.
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56F8346 Signal Pins
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Input Signal Description
SS0
129
Input
SPI 0 Slave Select -- SS0 is used in slave mode to indicate to the SPI module that the current transfer is to be received. Port E GPIO -- This GPIO pin can be individually programmed as input or output pin. After reset, the default state is SS0. To deactivate the internal pull-up resistor, clear bit 7 in the GPIOE_PUR register.
(GPIOE7)
Input/ Output
Input
PHASEA1
6
Schmitt Input Schmitt Input/ Output Schmitt Input/ Output
Input
Phase A1 -- Quadrature Decoder 1 PHASEA input for decoder 1. TB0 -- Timer B Channel 0
(TB0)
Input
(SCLK1)
Input
SPI1 Serial Clock -- In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. To activate the SPI function, set the PHSA_ALT bit in the SIM_GPS register. For details, see Section 6.5.8. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PHASEA1. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOC_PUR register.
(GPIOC0)
Schmitt Input/ Output
Input
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Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Input Signal Description
PHASEB1
7
Schmitt Input Schmitt Input/ Output Schmitt Input/ Output
Phase B1 -- Quadrature Decoder 1 PHASEB input for decoder 1. TB1 -- Timer B Channel 1
(TB1)
Input
(MOSI1)
Input
SPI 1 Master Out/Slave In -- This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. To activate the SPI function, set the PHSB_ALT bit in the SIM_GPS register. For details, see Section 6.5.8. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PHASEB1. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOC_PUR register.
(GPIOC1)
Schmitt Input/ Output
Input
INDEX1
8
Schmitt Input Schmitt Input/ Output Schmitt Input/ Output
Input
Index1 -- Quadrature Decoder 1 INDEX input
(TB2)
Input
TB2 -- Timer B Channel 2
(MISO1)
Input
SPI1 Master In/Slave Out -- This serial data pin is an input to a master device and output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. To activate the SPI function, set the INDEX_ALT bit in the SIM_GPS register. For details, see Section 6.5.8. Port C GPIO -- This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is INDEX1. To deactivate the internal pull-up resistor, clear bit 2 in the GPIOC_PUR register.
(GPIOC2)
Schmitt Input/ Output
Input
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56F8346 Signal Pins
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Input Signal Description
HOME1
9
Schmitt Input Schmitt Input/ Output Schmitt Input
Home -- Quadrature Decoder 1 HOME input
(TB3)
Input
TB3 -- Timer B Channel 3
(SS1)
Input
SPI 1 Slave Select -- In the master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. To activate the SPI function, set the HOME_ALT bit in the SIM_GPS register. For details, see Section 6.5.8. Port C GPIO -- This GPIO pin can be individually programmed as input or output pin. After reset, the default state is HOME1. To deactivate the internal pull-up resistor, clear bit 3 in the GPIOC_PUR register.
(GPIOC3)
Schmitt Input/ Output
Input
PWMA0 PWMA1 PWMA2 PWMA3 PWMA4 PWMA5 ISA0 (GPIOC8) ISA1 (GPIOC9) ISA2 (GPIOC10)
62 64 65 67 68 70 113
Output
Tri-State
PWMA0 - 5 -- These are six PWMA outputs.
Schmitt Input
Input
ISA0 - 2 -- These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA. Port C GPIO -- These GPIO pins can be individually programmed as input or output pins. At reset, these pins default to ISA functionality. Deactivate pull-up by setting the appropriate bit of the GPIOC_PUR register. For details, see Section 6.5.8.
114 Schmitt Input/ Output
115
FAULTA0 FAULTtA1 FAULTA2
71 73 74
Input
Schmitt Input
FAULTA0 - A2 -- These three fault input pins are used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. To deactivate the internal pull-up resistor, set the PWMA0 bit in the SIM_PUDR register. For details, see Section 6.5.8.
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Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Tri-State Signal Description
PWMB0 PWMB1 PWMB2 PWMB3 PWMB4 PWMB5 ISB0 (GPIOD10) ISB1 (GPIOD11) ISB2 (GPIOD12)
34 35 36 39 40 41 50
Output
PWMB0 - 5 -- Six PWMB output pins.
Schmitt Input
Input
ISB0 - 2 -- These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMB. Port D GPIO -- These GPIO pins can be individually programmed as input or output pins. At reset, these pins default to ISA functionality. To deactivate the internal pull-up resistor, clear the appropriate bit of the GPIOD_PUR register. For details, see Section 6.5.8.
52 Schmitt Input/ Output
53
FAULTB0 FAULTB1 FAULTB2 FAULTB3 ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 VREFH
56 57 58 61 88 89 90 91 92 93 94 95 101
Schmitt Input
Input
FAULTB0 - 3 -- These four fault input pins are used for disabling selected PWMB outputs in cases where fault conditions originate off-chip. To deactivate the internal pull-up resistor, set the PWMB bit in the SIM_PUDR register. For details, see Section 6.5.8.
Input
Input
ANA0 - 3 -- Analog inputs to ADC A, channel 0
Input
Input
ANA4 - 7 -- Analog inputs to ADC A, channel 1
Input
Input
VREFH -- Analog reference voltage high. VREFH must be less than or equal to VDDA_ADC.
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56F8346 Signal Pins
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset I/O Signal Description
VREFP VREFMID VREFN VREFLO
100 99 98 97
I/O
VREFP, VREFMID & VREFN -- Internal pins for voltage reference which are brought off-chip so they can be bypassed. Connect to a 0.1F or low ESR capacitor.
Input
Input
VREFLO -- Analog reference voltage low. This should normally be connected to a low-noise VSSA. ANB0 - 3 -- Analog inputs to ADC B, channel 0
ANB0 ANB1 ANB2 ANB3 ANB4 ANB5 ANB6 ANB7 Temp_Sense
104 105 106 107 108 109 110 111 96
Input
Input
Input
Input
ANB4 - 7 -- Analog inputs to ADC B, channel 1
Output
Output
Temp Sense Diode -- This signal connects to an on-chip diode that can be connected to one of the ADC inputs and used to monitor the temperature of the die. Must be bypassed with a 0.01 F capacitor. CAN Receive Data -- This is the CAN input. This pin has an internal pull-up resistor. To deactivate the internal pull-up resistor, set the CAN bit in the SIM_PUDR register.
CAN_RX
127
Schmitt Input
Input
CAN_TX
126
Open Drain Output Schmitt Input/ Output Schmitt Input/ Outpu
Output
CAN Transmit Data -- CAN output
TC0
118
Input
TC0 -- Timer C Channel 0
(GPIOE8)
Port E GPIO -- These GPIO pins can be individually programmed as input or output pins. To deactivate the internal pull-up resistor, clear bit 8 of the GPIOE_PUR register.
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Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Input Signal Description
TD0 (GPIOE10) TD1 (GPIOE11)
116
Schmitt Input/ Output Schmitt Input/ Output
TD0 and TD1 -- Timer D Channels 0 and 1
117 Port E GPIO -- These GPIO pins can be individually programmed as input or output pins. At reset, these pins default to Timer functionality. To deactivate the internal pull-up resistor, clear the appropriate bit of the GPIOE_PUR register. See Section 6.5.6 for details.
IRQA IRQB
54 55
Schmitt Input
Input
External Interrupt Request A and B -- The IRQA and IRQB inputs are asynchronous external interrupt requests during Stop and Wait mode operation. During other operating modes, they are synchronized external interrupt requests, which indicate an external device is requesting service. They can be programmed to be level-sensitive or negative-edge-triggered. To deactivate the internal pull-up resistor, set the IRQ bit in the SIM_PUDR register. See Section 6.5.6 for details.
RESET
86
Schmitt Input
Input
Reset -- This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and the JTAG/EOnCE module must not be reset. In this case, assert RESET but do not assert TRST. Note: The internal Power-On Reset will assert on initial power-up. To deactivate the internal pull-up resistor, set the RESET bit in the SIM_PUDR register. See Section 6.5.6 for details.
RSTO
85
Output
Output
Reset Output -- This output reflects the internal reset state of the chip.
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56F8346 Signal Pins
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type State During Reset Input Signal Description
EXTBOOT
112
Schmitt Input
External Boot -- This input is tied to VDD to force the device to boot from off-chip memory (assuming that the on-chip Flash memory is not in a secure state). Otherwise, it is tied to ground. For details, see Table 4-4. Note: When this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the XBOOT bit of the SIM_PUDR; see Section 6.5.6.
EMI_MODE
143
Schmitt Input
Input
External Memory Mode -- The EMI_MODE input is internally tied low (to VSS). This device will boot from internal flash memory under normal operation. This function is also affected by EXTBOOT and the Flash security mode. For details, see Table 4-4. If a 20-bit address bus is not desired, then this pin is tied to ground. Note: When this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the EMI_MODE bit of the SIM_PUDR; see Section 6.5.6.
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Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design that apply to the 56F8346 part. Figure 3-1 shows the specific OCCS block diagram to reference from the OCCS chapter in the 56F8300 Peripheral User Manual.
CLKMODE XTAL
MUX
Crystal OSC
ZSRC
EXTAL
PLLCID
FREF
Prescaler CLK
PLLDB
PLL FOUT x (1 to 128)
FEEDBACK
PLLCOD
/ (1,2,4,8)
MSTR_OSC
Prescaler
/2
FOUT/2 Postscaler
/ (1,2,4,8)
Postscaler CLK
MUX
SYS_CLK_X2 Source to SIM
Bus Interface & Control
Bus Interface
Lock Detector Loss of Reference Clock Detector
LCK
Loss of Reference Clock Interrupt
Figure 3-1 OCCS Block Diagram
3.2 External Clock Operation
The 56F8346 system clock can be derived from an external crystal, ceramic resonator, or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic resonator, must be connected between the EXTAL and XTAL pins.
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External Clock Operation
3.2.1
Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 10-16. A recommended crystal oscillator circuit is shown in Figure 3-2. Follow the crystal supplier's recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Crystal Frequency = 4 - 8MHz (optimized for 8MHz)
EXTAL XTAL Rz
CLKMODE = 0
EXTAL XTAL Rz
Sample External Crystal Parameters: Rz = 750 K Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg
CL1
CL2
Figure 3-2 Connecting to a Crystal Oscillator
Note: The OCCS_COHL bit should be set to 1 when a crystal oscillator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in Section 5 of the 56F8300 Peripheral User Manual.
3.2.2
Ceramic Resonator (Default)
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-3. Refer to supplier's recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as close as possible to the EXTAL and XTAL pins.
Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 2 Terminal EXTAL Rz XTAL 3 Terminal EXTAL Rz XTAL Sample External Ceramic Resonator Parameters: Rz = 750 K
CL1
CL2 C1 C2
CLKMODE = 0
Figure 3-3 Connecting a Ceramic Resonator
Note: The OCCS_COHL bit must set to 0 when a ceramic resonator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in Section 5 of the 56F8300 Peripheral User Manual.
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3.2.3
External Clock Source
The recommended method of connecting an external clock is given in Figure 3-4. The external clock source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit high when using an external clock source as well.
56F8346 XTAL External Clock EXTAL VSS Note: When using an external clocking source with this configuration, the input "CLKMODE" should be high and the COHL bit in the OSCTL register should be set to 1.
Figure 3-4 Connecting an External Clock Signal
3.3 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the register definitions without the internal Relaxation Oscillator, since the 56F8346 does NOT contain this oscillator.
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Introduction
Part 4 Memory Map
4.1 Introduction
The 56F8346 device is a 16-bit motor-control chip based on the 56800E core. It uses a Harvard-style architecture with two independent memory spaces for data and program. On-chip RAM and Flash memories are used in both spaces. This section provides memory maps for: * Program Address Space, including the Interrupt Vector Table * Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for each device are summarized in Table 4-1. Flash memories' restrictions are identified in the "Use Restrictions" column of Table 4-1.
Table 4-1 Chip Memory Configurations
On-Chip Memory Program Flash Data Flash Program RAM Data RAM Program Boot Flash 56F8346 128KB 8KB 4KB 8KB 8KB Use Restrictions Erase/Program via Flash interface unit and word writes to CDBW Erase/Program via Flash interface unit and word writes to CDBW. Data Flash can be read via either CDBR or XDB2, but not by both simultaneously None None Erase/Program via Flash Interface unit and word to CDBW
4.2 Program Map
The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory map configurations that are possible at reset. After reset, the OMR MA bit can be changed and will have an effect on the P-space memory map, as shown in Table 4-3. Changing the OMR MB bit will have no effect.
Table 4-2 OMR MA/MB Value at Reset
OMR MB = Flash Secured State1, 2 0 0 1 1 OMR MA = EXTBOOT Pin 0 1 0 1 Chip Operating Mode
Mode 0 - Internal Boot; EMI is configured to use 16 address lines; Flash Memory is secured; external P-space is not allowed; the EOnCE is disabled Not valid; cannot boot externally if the Flash is secured and will actually configure to 00 state Mode 0 - Internal Boot; EMI is configured to use 16 address lines Mode 1 - External Boot; Flash Memory is not secured; EMI configuration is determined by the state of the EMI_MODE bit
1. This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset. 2. Changing MB in software will not affect Flash memory security.
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Table 4-3 Changing OMR MA Value During Normal Operation
OMR MA 0 1 Chip Operating Mode Use internal P-space memory map configuration Use external P-space memory map configuration - If MB = 0 at reset, changing this bit has no effect.
The 56F8346's external memory interface (EMI) can operate much like the 56F80x family's EMI, or it can be operated in a mode similar to that used on other products in the 56800E family. Initially, CS0 and CS1 are configured as PS and DS, in a mode compatible with earlier 56800 devices. Eighteen address lines are required to shadow the first 192K of internal program space when booting externally for development purposes. Therefore, the entire complement of on-chip memory cannot be accessed using a 16-bit 56800-compatible address bus. To address this situation, the EMI_MODE pin can be used to configure four GPIO pins as Address[19:16] upon reset (only one of these pins [A16] is usable in the 56F8346). The EMI_MODE pin also affects the reset vector address, as provided in Table 4-4. Additional pins must be configured as address or chip select signals to access addresses at P:$10 0000 and above.
Table 4-4 Program Memory Map at Reset
Mode 0 (MA = 0) Begin/End Address Internal Boot Internal Boot 16-Bit External Address Bus P:$1F FFFF P:$10 0000 P:$0F FFFF P:$03 0000 P:$02 FFFF P:$02 F800 P:$02 F7FF P:$02 1000 P:$02 0FFF P:$02 0000 On-Chip Program RAM 4KB Reserved 116KB Boot Flash 8KB COP Reset Address = 02 0002 Boot Location = 02 0000 External Program RAM5 Internal Program Flash 128KB Boot Flash 8KB COP Reset Address = 02 00026 (Not Used for Boot in this Mode) Boot Location = 02 00006 Internal Program Flash7 128KB External Program RAM COP Reset Address = 00 0002 Boot Location = 00 0000 External Program Memory5 Mode 11 (MA = 1) External Boot EMI_MODE = 02,3 16-Bit External Address Bus External Program Memory5 EMI_MODE = 14 20-Bit External Address Bus External Program Memory5 External Program RAM
P:$01 FFFF P:$01 0000 P:$00 FFFF P:$00 0000
1. If Flash Security Mode is enabled EXTBOOT Mode 1 cannot be used. See Security Features, Part 7. 2. This mode provides maximum compatibility with 56F80x parts while operating externally. 3. "EMI_MODE =0" when EMI_MODE pin is tied to ground at boot up.
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Interrupt Vector Table
4. "EMI_MODE =1" when EMI_MODE pin is tied to VDD at boot up. 5. Not accessible in reset configuration since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip selects) pins must be reconfigured before this external memory is accessible. 6. Booting from this external address allows prototyping of the internal Boot Flash. 7. The internal Program Flash is relocated in this mode making it accessible.
4.3 Interrupt Vector Table
Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The priority of an interrupt can be assigned to different levels, as indicated, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Section 5.6.12 for the reset value of the VBA. In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions.
Table 4-5 Interrupt Vector Table Contents1
Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function Reserved for Reset Overlay2 Reserved for COP Reset Overlay2 core core core core core core 2 3 4 5 6 7 3 3 3 3 1-3 1-3 P:$04 P:$06 P:$08 P:$0A P:$0C P:$0E Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access OnCE Step Counter OnCE Breakpoint Unit 0 Reserved core core core 9 10 11 1-3 1-3 1-3 P:$12 P:$14 P:$16 OnCE Trace Buffer OnCE Transmit Register Empty OnCE Receive Register Full Reserved Reserved core core core core core 14 15 16 17 18 2 1 0 0-2 0-2 P:$1C P:$1E P:$20 P:$22 P:$24 SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 IRQA IRQB
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Table 4-5 Interrupt Vector Table Contents1 (Continued)
Peripheral Vector Number Priority Level Vector Base Address + Reserved LVI PLL FM FM FM 20 21 22 23 24 0-2 0-2 0-2 0-2 0-2 P:$28 P:$2A P:$2C P:$2E P:$30 Low Voltage Detector (power sense) PLL FM Error Interrupt FM Command Complete FM Command, data and address Buffers Empty Reserved FLEXCAN FLEXCAN FLEXCAN FLEXCAN GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA 26 27 28 29 30 31 32 33 34 35 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 P:$34 P:$36 P:$38 P:$3A P:$3C P:$3E P:$40 P:$42 P:$44 P:$46 FLEXCAN Bus Off FLEXCAN Error FLEXCAN Wake Up FLEXCAN Message Buffer Interrupt GPIO F GPIO E GPIO D GPIO C GPIO B GPIO A Reserved Reserved SPI1 SPI1 SPI0 SPI0 SCI1 SCI1 38 39 40 41 42 43 0-2 0-2 0-2 0-2 0-2 0-2 P:$4C P:$4E P:$50 P:$52 P:$54 P:$56 SPI 1 Receiver Full SPI 1 Transmitter Empty SPI 0 Receiver Full SPI 0 Transmitter Empty SCI 1 Transmitter Empty SCI 1Transmitter Idle Reserved SCI1 SCI1 DEC1 DEC1 DEC0 DEC0 45 46 47 48 49 50 0-2 0-2 0-2 0-2 0-2 0-2 P:$5A P:$5C P:$5E P:$60 P:$62 P:$64 SCI 1 Receiver Error SCI 1 Receiver Full Quadrature Decoder #1 Home Switch or Watchdog Quadrature Decoder #1 INDEX Pulse Quadrature Decoder #0 Home Switch or Watchdog Quadrature Decoder #0 INDEX Pulse Reserved TMRD TMRD 52 53 0-2 0-2 P:$68 P:$6A Timer D Channel 0 Timer D Channel 1 Interrupt Function
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Interrupt Vector Table
Table 4-5 Interrupt Vector Table Contents1 (Continued)
Peripheral TMRD TMRD TMRC TMRC TMRC TMRC TMRB TMRB TMRB TMRB TMRA TMRA TMRA TMRA SCI0 SCI0 Vector Number 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Priority Level 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 Vector Base Address + P:$6C P:$6E P:$70 P:$72 P:$74 P:$76 P:$78 P:$7A P:$7C P:$7E P:$80 P:$82 P:$84 P:$86 P:$88 P:$8A Timer D Channel 2 Timer D Channel 3 Timer C Channel 0 Timer C Channel 1 Timer C Channel 2 Timer C Channel 3 Timer B Channel 0 Timer B Channel 1 Timer B Channel 2 Timer B Channel 3 Timer A Channel 0 Timer A Channel 1 Timer A Channel 2 Timer A Channel 3 SCI 0 Transmitter Empty SCI 0 Transmitter Idle Reserved SCI0 SCI0 ADCB ADCA ADCB ADCA PWMB PWMA PWMB PWMA core 71 72 73 74 75 76 77 78 79 80 81 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 -1 P:$8E P:$90 P:$92 P:$94 P:$96 P:$98 P:$9A P:$9C P:$9E P:$A0 P:$A2 SCI 0 Receiver Error SCI 0 Receiver Full ADC B Conversion Compete ADC A Conversion Complete ADC B Zero Crossing of Limit Error ADC A Zero Crossing of Limit Error Reload PWM B Reload PWM A PWM B Fault PWM A Fault SW Interrupt LP Interrupt Function
1. Two words are allocated for each entry in the Vector table. This does not allow the full address range to be referenced from the Vector table, providing only 19 bits of address. 2. If the VBA is set to 0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the chip reset addresses; therefore, these locations are not interrupt vectors.
2.
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4.4 Data Map
Table 4-6 Data Memory Map1
Begin/End Address X:$FF FFFF X:$FF FF00 X:$FF FEFF X:$01 0000 X:$00 FFFF X:$00 F000 X:$00 EFFF X:$00 2000 X:$00 1FFF X:$00 1000 X:$00 0FFF X:$00 0000 EX = 02 EOnCE 256 locations allocated External Memory On-Chip Peripherals 4096 location allocated External Memory On-Chip Data Flash 8KB On-Chip Data RAM 8KB3 EX = 1 EOnCE 256 locations allocated External Memory On-Chip Peripherals 4096 location allocated External Memory
1. All addresses are 16-bit Word addresses, not byte addresses. 2. In the Operation Mode Register (OMR). 3. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle long-word operations.
4.5 Flash Memory Map
Figure 4-1 illustrates the Flash Memory (FM) map on the system bus. The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides on the Data Memory buses and is controlled separately, having its own set of banked registers. The top nine words of the Program Memory Flash are treated as special memory locations. The content of these words is used to control the operation of the Flash Controller. Because these words are part of the Flash Memory content, their state is maintained during power-down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual. In the 56F8346, these configuration parameters are located between $00_FFF7 and $00_FFFF.
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Flash Memory Map
Program Memory
(BOOT_FLASH_START + $1FFF) (BOOT_FLASH_START = $02_0000)
Data Memory
FM_BASE + $14
8KB Boot
Banked Registers Unbanked Registers
FM_BASE + $00
Reserved
DATA_FLASH_START + $0FFF DATA_FLASH_START + $0000
8KB 8KB
(PROG_FLASH_START + $00_FFFF) (PROG_FLASH_START + $00_FFF7) (PROG_FLASH_START + $00_FFF6)
Configure Field
(FM_PROG_MEM_TOP = $00_FFFF)
Block 0 Odd Block 0 Even ...
BLOCK 0 Odd (2 Bytes) $00_0003 BLOCK 0 Even (2 Bytes) $00_0002 BLOCK 0 Odd (2 Bytes) $00_0001 BLOCK 0 Even (2 Bytes) $00_0000
128K Bytes
(PROG_FLASH_START = $00_0000)
Figure 4-1 Flash Array Memory Maps
Table 4-7 shows the page and sector sizes used within each Flash memory block on the chip.
Table 4-7. Flash Memory Partitions
Flash Size Program Flash Data Flash Boot Flash 128KB 8KB 8KB Sectors 16 16 4 Sector Size 4K x 16 bits 256 x 16 bits 1K x 16 bits Page Size 512 x 16 bits 256 x 16 bits 256 x 16 bits
Please see 56F8300 Peripheral User Manual for additional Flash information.
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4.6 EOnCE Memory Map
Table 4-8 EOnCE Memory Map
Address Register Acronym Reserved X:$FF FF8A OESCR External Signal Control Register Reserved X:$FF FF8E OBCNTR Breakpoint Unit [0] Counter Reserved X:$FF FF90 X:$FF FF91 X:$FF FF92 X:$FF FF93 X:$FF FF94 X:$FF FF95 X:$FF FF96 X:$FF FF97 X:$FF FF98 X:$FF FF99 X:$FF FF9A X:$FF FF9B X:$FF FF9C X:$FF FF9D X:$FF FF9E X:$FF FF9F :X:$FF FFA0 OBMSK (32 bits) -- OBAR2 (32 bits) -- OBAR1 (24 bits) -- OBCR (24 bits) -- OTB (21-24 bits/stage) -- OTBPR (8 bits) OTBCR OBASE (8 bits) OSR OSCNTR (24 bits) -- OCR (bits) Breakpoint 1 Unit [0] Mask Register Breakpoint 1 Unit [0] Mask Register Breakpoint 2 Unit [0] Address Register Breakpoint 2 Unit [0] Address Register Breakpoint 1 Unit [0] Address Register Breakpoint 1 Unit [0] Address Register Breakpoint Unit [0] Control Register Breakpoint Unit [0] Control Register Trace Buffer Register Stages Trace Buffer Register Stages Trace Buffer Pointer Register Trace Buffer Control Register Peripheral Base Address Register Status Register Instruction Step Counter Instruction Step Counter Control Register Reserved X:$FF FFFC X:$FF FFFD X:$FF FFFE X:$FF FFFF OCLSR (8 bits) OTXRXSR (8 bits) OTX/ORX (32 bits) OTX1/ORX1 Core Lock/Unlock Status Register Transmit and Receive Status and Control Register Transmit Register / Receive Register Transmit Register Upper Word Receive Register Upper Word Register Name
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Peripheral Memory Mapped Registers
4.7 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read/written using word accesses only. Table 4-9 summarizes base addresses for the set of peripherals on the 56F8346 device. Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals.
Table 4-9 Data Memory Peripheral Base Address Map Summary
Peripheral External Memory Interface Timer A Timer B Timer C Timer D PWM A PWM B Quadrature Decoder 0 Quadrature Decoder 1 ITCN ADC A ADC B Temperature Sensor SCI #0 SCI #1 SPI #0 SPI #1 COP PLL, OSC GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E GPIO Port F SIM Power Supervisor FM FlexCAN EMI TMRA TMRB TMRC TMRD PWMA PWMB DEC0 DEC1 ITCN ADCA ADCB TSENSOR SCI0 SCI1 SPI0 SPI1 COP CLKGEN GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF SIM LVI FM FC Prefix Base Address X:$00 F020 X:$00 F040 X:$00 F080 X:$00 F0C0 X:$00 F100 X:$00 F140 X:$00 F160 X:$00 F180 X:$00 F190 X:$00 F1A0 X:$00 F200 X:$00 F240 X:$00 F270 X:$00 F280 X:$00 F290 X:$00 F2A0 X:$00 F2B0 X:$00 F2C0 X:$00 F2D0 X:$00 F2E0 X:$00 F300 X:$00 F310 X:$00 F320 X:$00 F330 X:$00 F340 X:$00 F350 X:$00 F360 X:$00 F400 X:$00 F800 Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38
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Table 4-10 External Memory Integration Registers Address Map (EMI_BASE = $00F020)
Register Acronym CSBAR 0 CSBAR 1 CSBAR 2 CSBAR 3 CSBAR 4 CSBAR 5 CSBAR 6 CSBAR 7 CSOR 0 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 Register Description Chip Select Base Address Register 0 Chip Select Base Address Register 1 Chip Select Base Address Register 2 Chip Select Base Address Register 3 Chip Select Base Address Register 4 Chip Select Base Address Register 5 Chip Select Base Address Register 6 Chip Select Base Address Register 7 Chip Select Option Register 0 0x5FCB programmed for chip select for program space, word wide, read and write, 11 waits 0x5FAB programmed for chip select for data space, word wide, read and write, 11 waits Reset Value
CSOR 1
$9
Chip Select Option Register 1
CSOR 2 CSOR 3 CSOR 4 CSOR 5 CSOR 6 CSOR 7 CSTC 0 CSTC 1 CSTC 2 CSTC 3 CSTC 4 CSTC 5 CSTC 6 CSTC 7 BCR
$A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18
Chip Select Option Register 2 Chip Select Option Register 3 Chip Select Option Register 4 Chip Select Option Register 5 Chip Select Option Register 6 Chip Select Option Register 7 Chip Select Timing Control Register 0 Chip Select Timing Control Register 1 Chip Select Timing Control Register 2 Chip Select Timing Control Register 3 Chip Select Timing Control Register 4 Chip Select Timing Control Register 5 Chip Select Timing Control Register 6 Chip Select Timing Control Register 7 Bus Control Register 0x016B sets the default number of wait states to 11 for both read and write accesses
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Peripheral Memory Mapped Registers
Table 4-11 Quad Timer A Registers Address Map (TMRA_BASE = $00F040)
Register Acronym TMRA0_CMP1 TMRA0_CMP2 TMRA0_CAP TMRA0_LOAD TMRA0_HOLD TMRA0_CNTR TMRA0_CTRL TMRA0_SCR TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_COMSCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserve TMRA1_CMP1 TMRA1_CMP2 TMRA1_CAP TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register
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Table 4-11 Quad Timer A Registers Address Map (TMRA_BASE = $00F040) (Continued)
Register Acronym Address Offset Reserved TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP TMRA3_LOAD TMRA3_HOLD TMRA3_CNTR TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSC $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Register Description
Table 4-12 Quad Timer B Registers Address Map (TMRB_BASE = $00F080)
Register Acronym TMRB0_CMP1 TMRB0_CMP2 TMRB0_CAP TMRB0_LOAD TMRB0_HOLD TMRB0_CNTR TMRB0_CTRL TMRB0_SCR TMRB0_CMPLD1 TMRB0_CMPLD2 TMRB0_COMSCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRB1_CMP1 TMRB1_CMP2 TMRB1_CAP TMRB1_LOAD TMRB1_HOLD TMRB1_CNTR TMRB1_CTRL TMRB1_SCR $10 $11 $12 $13 $14 $15 $16 $17 Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register
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Table 4-12 Quad Timer B Registers Address Map (TMRB_BASE = $00F080) (Continued)
Register Acronym TMRB1_CMPLD1 TMRB1_CMPLD2 TMRB1_COMSCR Address Offset $18 $19 $1A Register Description Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRB2_CMP1 TMRB2_CMP2 TMRB2_CAP TMRB2_LOAD TMRB2_HOLD TMRB2_CNTR TMRB2_CTRL TMRB2_SCR TMRB2_CMPLD1 TMRB2_CMPLD2 TMRB2_COMSCR $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRB3_CMP1 TMRB3_CMP2 TMRB3_CAP TMRB3_LOAD TMRB3_HOLD TMRB3_CNTR TMRB3_CTRL TMRB3_SCR TMRB3_CMPLD1 TMRB3_CMPLD2 TMRB3_COMSCR $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register
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Table 4-13 Quad Timer C Registers Address Map (TMRC_BASE = $00F0C0)
Register Acronym TMRC0_CMP1 TMRC0_CMP2 TMRC0_CAP TMRC0_LOAD TMRC0_HOLD TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 TMRC1_COMSCR $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2
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Table 4-13 Quad Timer C Registers Address Map (TMRC_BASE = $00F0C0) (Continued)
Register Acronym TMRC2_COMSCR Address Offset $2A Register Description Comparator Status and Control Register Reserved TMRC3_CMP1 TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register
Table 4-14 Quad Timer D Registers Address Map (TMRD_BASE = $00F100)
Register Acronym TMRD0_CMP1 TMRD0_CMP2 TMRD0_CAP TMRD0_LOAD TMRD0_HOLD TMRD0_CNTR TMRD0_CTRL TMRD0_SCR TMRD0_CMPLD1 TMRD0_CMPLD2 TMRD0_COMSCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRD1_CMP1 TMRD1_CMP2 TMRD1_CAP TMRD1_LOAD TMRD1_HOLD TMRD1_CNTR TMRD1_CTRL $10 $11 $12 $13 $14 $15 $16 Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register
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Table 4-14 Quad Timer D Registers Address Map (TMRD_BASE = $00F100) (Continued)
Register Acronym TMRD1_SCR TMRD1_CMPLD1 TMRD1_CMPLD2 TMRD1_COMSCR Address Offset $17 $18 $19 $1A Register Description Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRD2_CMP1 TMRD2_CMP2 TMRD2_CAP TMRD2_LOAD TMRD2_HOLD TMRD2_CNTR TMRD2_CTRL TMRD2_SCR TMRD2_CMPLD1 TMRD2_CMPLD2 TMRD2_COMSCR $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register Reserved TMRD3_CMP1 TMRD3_CMP2 TMRD3_CAP TMRD3_LOAD TMRD3_HOLD TMRD3_CNTR TMRD3_CTRL TMRD3_SCR TMRD3_CMPLD1 TMRD3_CMPLD2 TMRD3_COMSCR $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A Compare Register 1 Compare Register 2 Capture Register Load Register Hold Register Counter Register Control Register Status and Control Register Comparator Load Register 1 Comparator Load Register 2 Comparator Status and Control Register
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Table 4-15 Pulse Width Modulator A Registers Address Map (PWMA_BASE = $00F140)
Register Acronym PWMA_PMCTL PWMA_PMFCTL PWMA_PMFSA PWMA_PMOUT PWMA_PMCNT PWMA_PWMCM PWMA_PWMVAL0 PWMA_PWMVAL1 PWMA_PWMVAL2 PWMA_PWMVAL3 PWMA_PWMVAL4 PWMA_PWMVAL5 PWMA_PMDEADTM PWMA_PMDISMAP1 PWMA_PMDISMAP2 PWMA_PMCFG PWMA_PMCCR PWMA_PMPORT PWMA_PMICCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 Control Register Fault Control Register Fault Status Acknowledge Register Output Control Register Counter Register Counter Modulo Register Value Register 0 Value Register 1 Value Register 2 Value Register 3 Value Register 4 Value Register 5 Dead Time Register Disable Mapping Register 1 Disable Mapping Register 2 Configure Register Channel Control Register Port Register PWM Internal Correction Control Register Register Description
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Table 4-16 Pulse Width Modulator B Registers Address Map (PWMB_BASE = $00F160)
Register Acronym PWMB_PMCTL PWMB_PMFCTL PWMB_PMFSA PWMB_PMOUT PWMB_PMCNT PWMB_PWMCM PWMB_PWMVAL0 PWMB_PWMVAL1 PWMB_PWMVAL2 PWMB_PWMVAL3 PWMB_PWMVAL4 PWMB_PWMVAL5 PWMB_PMDEADTM PWMB_PMDISMAP1 PWMB_PMDISMAP2 PWMB_PMCFG PWMB_PMCCR PWMB_PMPORT PWMB_PMICCR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 Control Register Fault Control Register Fault Status Acknowledge Register Output Control Register Counter Register Counter Modulo Register Value Register 0 Value Register 1 Value Register 2 Value Register 3 Value Register 4 Value Register 5 Dead Time Register Disable Mapping Register 1 Disable Mapping Register 2 Configure Register Channel Control Register Port Register PWM Internal Correction Control Register Register Description
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Table 4-17 Quadrature Decoder 0 Registers Address Map (DEC0_BASE = $00F180)
Register Acronym DEC0_DECCR DEC0_FIR DEC0_WTR DEC0_POSD DEC0_POSDH DEC0_REV DEC0_REVH DEC0_UPOS DEC0_LPOS DEC0_UPOSH DEC0_LPOSH DEC0_UIR DEC0_LIR DEC0_IMR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D Register Description Decoder Control Register Filter Interval Register Watchdog Timeout Register Position Difference Counter Register Position Difference Counter Hold Register Revolution Counter Register Revolution Hold Register Upper Position Counter Register Lower Position Counter Register Upper Position Hold Register Lower Position Hold Register Upper Initialization Register Lower Initialization Register Input Monitor Register
Table 4-18 Quadrature Decoder 1 Registers Address Map (DEC1_BASE = $00F190)
Register Acronym DEC1_DECCR DEC1_FIR DEC1_WTR DEC1_POSD DEC1_POSDH DEC1_REV DEC1_REVH DEC1_UPOS DEC1_LPOS DEC1_UPOSH DEC1_LPOSH DEC1_UIR DEC1_LIR DEC1_IMR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D Register Description Decoder Control Register Filter Interval Register Watchdog Timeout Register Position Difference Counter Register Position Difference Counter Hold Register Revolution Counter Register Revolution Hold Register Upper Position Counter Register Lower Position Counter Register Upper Position Hold Register Lower Position Hold Register Upper Initialization Register Lower Initialization Register Input Monitor Register
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Table 4-19 Interrupt Control Registers Address Map (ITCN_BASE = $00F1A0)
Register Acronym IPR 0 IPR 1 IPR 2 IPR 3 IPR 4 IPR 5 IPR 6 IPR 7 IPR 8 IPR 9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP 0 IRQP 1 IRQP 2 IRQP 3 IRQP 4 IRQP 5 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C ICTL $1D Register Description Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Interrupt Priority Register 7 Interrupt Priority Register 8 Interrupt Priority Register 9 Vector Base Address Register Fast Interrupt Match Register 0 Fast Interrupt Vector Address Low 0 Register Fast Interrupt Vector Address High 0 Register Fast Interrupt Match Register 1 Fast Interrupt Vector Address Low 1 Register Fast Interrupt Vector Address High 1 Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 IRQ Pending Register 3 IRQ Pending Register 4 IRQ Pending Register 5 Reserved Reserved Reserved Reserved Reserved Reserved Interrupt Control Register
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Table 4-20 Analog to Digital Converter Registers Address Map (ADCA_BASE = $00F200)
Register Acronym ADCA_CR 1 ADCA_CR 2 ADCA_ZCC ADCA_LST 1 ADCA_LST 2 ADCA_SDIS ADCA_STAT ADCA_LSTAT ADCA_ZCSTAT ADCA_RSLT 0 ADCA_RSLT 1 ADCA_RSLT 2 ADCA_RSLT 3 ADCA_RSLT 4 ADCA_RSLT 5 ADCA_RSLT 6 ADCA_RSLT 7 ADCA_LLMT 0 ADCA_LLMT 1 ADCA_LLMT 2 ADCA_LLMT 3 ADCA_LLMT 4 ADCA_LLMT 5 ADCA_LLMT 6 ADCA_LLMT 7 ADCA_HLMT 0 ADCA_HLMT 1 ADCA_HLMT 2 ADCA_HLMT 3 ADCA_HLMT 4 ADCA_HLMT 5 ADCA_HLMT 6 ADCA_HLMT 7 ADCA_OFS 0 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $20 $21 Register Description Control Register 1 Control Register 2 Zero Crossing Control Register Channel List Register 1 Channel List Register 2 Sample Disable Register Status Register Limit Status Register Zero Crossing Status Register Result Register 0 Result Register 1 Result Register 2 Result Register 3 Result Register 4 Result Register 5 Result Register 6 Result Register 7 Low Limit Register 0 Low Limit Register 1 Low Limit Register 2 Low Limit Register 3 Low Limit Register 4 Low Limit Register 5 Low Limit Register 6 Low Limit Register 7 High Limit Register 0 High Limit Register 1 High Limit Register 2 High Limit Register 3 High Limit Register 4 High Limit Register 5 High Limit Register 6 High Limit Register 7 Offset Register 0
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Table 4-20 Analog to Digital Converter Registers Address Map (ADCA_BASE = $00F200) (Continued)
Register Acronym ADCA_OFS 1 ADCA_OFS 2 ADCA_OFS 3 ADCA_OFS 4 ADCA_OFS 5 ADCA_OFS 6 ADCA_OFS 7 ADCA_POWER ADCA_CAL Address Offset $22 $23 $24 $25 $26 $27 $28 $29 $2A Register Description Offset Register 1 Offset Register 2 Offset Register 3 Offset Register 4 Offset Register 5 Offset Register 6 Offset Register 7 Power Control Register ADC Calibration Register
Table 4-21 Analog to Digital Converter Registers Address Map (ADCB_BASE = $00F240)
Register Acronym ADCB_CR 1 ADCB_CR 2 ADCB_ZCC ADCB_LST 1 ADCB_LST 2 ADCB_SDIS ADCB_STAT ADCB_LSTAT ADCB_ZCSTAT ADCB_RSLT 0 ADCB_RSLT 1 ADCB_RSLT 2 ADCB_RSLT 3 ADCB_RSLT 4 ADCB_RSLT 5 ADCB_RSLT 6 ADCB_RSLT 7 ADCB_LLMT 0 ADCB_LLMT 1 ADCB_LLMT 2 ADCB_LLMT 3 ADCB_LLMT 4 Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 Register Description Control Register 1 Control Register 2 Zero Crossing Control Register Channel List Register 1 Channel List Register 2 Sample Disable Register Status Register Limit Status Register Zero Crossing Status Register Result Register 0 Result Register 1 Result Register 2 Result Register 3 Result Register 4 Result Register 5 Result Register 6 Result Register 7 Low Limit Register 0 Low Limit Register 1 Low Limit Register 2 Low Limit Register 3 Low Limit Register 4
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Table 4-21 Analog to Digital Converter Registers Address Map (ADCB_BASE = $00F240) (Continued)
Register Acronym ADCB_LLMT 5 ADCB_LLMT 6 ADCB_LLMT 7 ADCB_HLMT 0 ADCB_HLMT 1 ADCB_HLMT 2 ADCB_HLMT 3 ADCB_HLMT 4 ADCB_HLMT 5 ADCB_HLMT 6 ADCB_HLMT 7 ADCB_OFS 0 ADCB_OFS 1 ADCB_OFS 2 ADCB_OFS 3 ADCB_OFS 4 ADCB_OFS 5 ADCB_OFS 6 ADCB_OFS 7 ADCB_POWER ADCB_CAL Address Offset $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A Register Description Low Limit Register 5 Low Limit Register 6 Low Limit Register 7 High Limit Register 0 High Limit Register 1 High Limit Register 2 High Limit Register 3 High Limit Register 4 High Limit Register 5 High Limit Register 6 High Limit Register 7 Offset Register 0 Offset Register 1 Offset Register 2 Offset Register 3 Offset Register 4 Offset Register 5 Offset Register 6 Offset Register 7 Power Control Register ADC Calibration Register
Table 4-22 Temperature Sensor Register Address Map (TSENSOR_BASE = $00F270)
Register Acronym TSENSOR_CNTL Address Offset $0 Control Register Register Description
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Peripheral Memory Mapped Registers
Table 4-23 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00F280)
Register Acronym SCI0_SCIBR SCI0_SCICR Address Offset $0 $1 Register Description Baud Rate Register Control Register Reserved SCI0_SCISR SCI0_SCIDR $3 $4 Status Register Data Register
Table 4-24 Serial Communication Interface 1 Registers Address Map (SCI1_BASE = $00F290)
Register Acronym SCI1_SCIBR SCI1_SCICR Address Offset $0 $1 Register Description Baud Rate Register Control Register Reserved SCI1_SCISR SCI1_SCIDR $3 $4 Status Register Data Register
Table 4-25 Serial Peripheral Interface 0 Registers Address Map (SPI0_BASE = $00F2A0)
Register Acronym SPI0_SPSCR SPI0_SPDSR SPI0_SPDRR SPI0_SPDTR Address Offset $0 $1 $2 $3 Register Description Status and Control Register Data Size Register Data Receive Register Data Transmitter Register
Table 4-26 Serial Peripheral Interface 1 Registers Address Map (SPI1_BASE = $00F2B0)
Register Acronym SPI1_SPSCR SPI1_SPDSR SPI1_SPDRR SPI1_SPDTR Address Offset $0 $1 $2 $3 Register Description Status and Control Register Data Size Register Data Receive Register Data Transmitter Register
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Table 4-27 Computer Operating Properly Registers Address Map (COP_BASE = $00F2C0)
Register Acronym COPCTL COPTO COPCTR Address Offset $0 $1 $2 Control Register Time Out Register Counter Register Register Description
Table 4-28 Clock Generation Module Registers Address Map (CLKGEN_BASE = $00F2D0)
Register Acronym PLLCR PLLDB PLLSR Address Offset $0 $1 $2 Control Register Divide-By Register Status Register Reserved SHUTDOWN OSCTL $4 $5 Shutdown Register Oscillator Control Register Register Description
Table 4-29 GPIOA Registers Address Map (GPIOA_BASE = $00F2E0)
Register Acronym GPIOA_PUR GPIOA_DR GPIOA_DDR GPIOA_PER GPIOA_IAR GPIOA_IENR GPIOA_IPOLR GPIOA_IPR GPIOA_IESR GPIOA_PPMODE GPIOA_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 3FFF 0 x 0000 0 x 0000 0 x 3FFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 3FFF -
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Table 4-30 GPIOB Registers Address Map (GPIOB_BASE = $00F300)
Register Acronym GPIOB_PUR GPIOB_DR GPIOB_DDR GPIOB_PER GPIOB_IAR GPIOB_IENR GPIOB_IPOLR GPIOB_IPR GPIOB_IESR GPIOB_PPMODE GPIOB_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 00FF 0 x 0000 0 x 0000 0 x 0000 or 0 x 000F 1 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 00FF -
1. Determined by EMI_MODE and EXTBOOT. Can be 0x00 or 0x0F, depending on address pin configuration. See Table 4-4.
Table 4-31 GPIOC Registers Address Map (GPIOC_BASE = $00F310)
Register Acronym GPIOC_PUR GPIOC_DR GPIOC_DDR GPIOC_PER GPIOC_IAR GPIOC_IENR GPIOC_IPOLR GPIOC_IPR GPIOC_IESR GPIOC_PPMODE GPIOC_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 07FF 0 x 0000 0 x 0000 0 x 07FF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 07FF -
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Table 4-32 GPIOD Registers Address Map (GPIOD_BASE = $00F320)
Register Acronym GPIOD_PUR GPIOD_DR GPIOD_DDR GPIOD_PER GPIOD_IAR GPIOD_IENR GPIOD_IPOLR GPIOD_IPR GPIOD_IESR GPIOD_PPMODE GPIOD_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 1FFF 0 x 0000 0 x 0000 0 x 1FC0 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 1FFF -
Table 4-33 GPIOE Registers Address Map (GPIOE_BASE = $00F330)
Register Acronym GPIOE_PUR GPIOE_DR GPIOE_DDR GPIOE_PER GPIOE_IAR GPIOE_IENR GPIOE_IPOLR GPIOE_IPR GPIOE_IESR GPIOE_PPMODE GPIOE_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x 3FFF 0 x 0000 0 x 0000 0 x 3FFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 3FFF -
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Table 4-34 GPIOF Registers Address Map (GPIOF_BASE = $00F340)
Register Acronym GPIOF_PUR GPIOF_DR GPIOF_DDR GPIOF_PER GPIOF_IAR GPIOF_IENR GPIOF_IPOLR GPIOF_IPR GPIOF_IESR GPIOF_PPMODE GPIOF_RAWDATA Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A Register Description Pull-up Enable Register Data Register Data Direction Register Peripheral Enable Register Interrupt Assert Register Interrupt Enable Register Interrupt Polarity Register Interrupt Pending Register Interrupt Edge-Sensitive Register Push-Pull Mode Register Raw Data Input Register Reset Value 0 x FFFF 0 x 0000 0 x 0000 0 x FFFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x FFFF -
Table 4-35 System Integration Module Registers Address Map (SIM_BASE = $00F350)
Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR Address Offset $0 $1 $2 $3 $4 $5 $6 $7 $8 Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half JTAG ID Least Significant Half JTAG ID Pull-up Disable Register Reserved SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL $A $B $C $D $E Clock Out Select Register Quad Decoder 1 / Timer B / SPI 1 Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register Register Description
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Table 4-36 Power Supervisor Registers Address Map (LVI_BASE = $00F360)
Register Acronym LVI_CONTROL LVI_STATUS Address Offset $0 $1 Control Register Status Register Register Description
Table 4-37 Flash Module Registers Address Map (FM_BASE = $00F400)
Register Acronym FMCLKD FMMCR Address Offset $0 $1 Register Description Clock Divider Register Module Control Register Reserved FMSECH FMSECL FMMNTR $3 $4 $5 Security High Half Register Security Low Half Register Monitor Data Register Reserved FMPROT FMPROTB $10 $11 Protection Register (Banked) Protection Boot Register (Banked) Reserved FMUSTAT FMCMD FMCTL $13 $14 $15 User Status Register (Banked) Command Register (Banked) Control Register (Banked) Reserved FMIFROPT 0 $1A 16-Bit Information Option Register 0 Hot temperature ADC reading of Temp Sense; value set during factory test 16-Bit Information Option Register 1 Not used 16-Bit Information Option Register 2 Room temperature ADC reading of Temp Sense; value set during factory test
FMIFROPT 1 FMIFROPT 2
$1B $1C
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Table 4-38 FlexCAN Registers Address Map (FC_BASE = $00F800)
Register Acronym FCMCR Address Offset $0 Register Description Module Configuration Register Reserved FCCTL0 FCCTL1 FCTMR FCMAXMB FCIMASK2 FCRXGMASK_H FCRXGMASK_L FCRX14MASK_H FCRX14MASK_L FCRX15MASK_H FCRX15MASK_L $3 $4 $5 $6 $7 $8 $9 $A $B $C $D Control Register 0 Register Control Register 1 Register Free Running Timer Register Maximum Message Buffer Configuration Register Interrupt Masks 2 Register Receive Global Mask High Register Receive Global Mask Low Register Receive Buffer 14 Mask High Register Receive Buffer 14 Mask Low Register Receive Buffer 15 Mask High Register Receive Buffer 15 Mask Low Register Reserved FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS $10 $11 $12 $13 Error and Status Register Interrupt Masks 1 Register Interrupt Flags 1 Register Receive and Transmit Error Counters Register Reserved FCIFLAG 2 $1B Interrupt Flags 2 Register Reserved FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA $40 $41 $42 $43 $44 $45 $46 Message Buffer 0 Control/Status Register Message Buffer 0 ID High Register Message Buffer 0 ID Low Register Message Buffer 0 Data Register Message Buffer 0 Data Register Message Buffer 0 Data Register Message Buffer 0 Data Register Reserved FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA $48 $49 $4A $4B $4C $4D $4E Message Buffer 1 Control/Status Register Message Buffer 1 ID High Register Message Buffer 1 ID Low Register Message Buffer 1 Data Register Message Buffer 1 Data Register Message Buffer 1 Data Register Message Buffer 1 Data Register
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Table 4-38 FlexCAN Registers Address Map (FC_BASE = $00F800) (Continued)
Register Acronym Address Offset Reserved FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA FCMB2_DATA FCMB2_DATA FCMB2_DATA $50 $51 $52 $53 $54 $55 $56 Message Buffer 2 Control/Status Register Message Buffer 2 ID High Register Message Buffer 2 ID Low Register Message Buffer 2 Data Register Message Buffer 2 Data Register Message Buffer 2 Data Register Message Buffer 2 Data Register Reserved FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA $58 $59 $5A $5B $5C $5D $5E Message Buffer 3 Control/Status Register Message Buffer 3 ID High Register Message Buffer 3 ID Low Register Message Buffer 3 Data Register Message Buffer 3 Data Register Message Buffer 3 Data Register Message Buffer 3 Data Register Reserved FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB4_DATA $60 $61 $62 $63 $64 $65 $66 Message Buffer 4 Control/Status Register Message Buffer 4 ID High Register Message Buffer 4 ID Low Register Message Buffer 4 Data Register Message Buffer 4 Data Register Message Buffer 4 Data Register Message Buffer 4 Data Register Reserved FCMB5_CONTROL FCMB5_ID_HIGH FCMB5_ID_LOW FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB5_DATA $68 $69 $6A $6B $6C $6D $6E Message Buffer 5 Control/Status Register Message Buffer 5 ID High Register Message Buffer 5 ID Low Register Message Buffer 5 Data Register Message Buffer 5 Data Register Message Buffer 5 Data Register Message Buffer 5 Data Register Reserved FCMB6_CONTROL FCMB6_ID_HIGH $70 $71 Message Buffer 6 Control/Status Register Message Buffer 6 ID High Register Register Description
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Table 4-38 FlexCAN Registers Address Map (FC_BASE = $00F800) (Continued)
Register Acronym FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB6_DATA Address Offset $72 $73 $74 $75 $76 Register Description Message Buffer 6 ID Low Register Message Buffer 6 Data Register Message Buffer 6 Data Register Message Buffer 6 Data Register Message Buffer 6 Data Register Reserved FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA $78 $79 $7A $7B $7C $7D $7E Message Buffer 7 Control/Status Register Message Buffer 7 ID High Register Message Buffer 7 ID Low Register Message Buffer 7 Data Register Message Buffer 7 Data Register Message Buffer 7 Data Register Message Buffer 7 Data Register Reserved FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB8_DATA $80 $81 $82 $83 $84 $85 $86 Message Buffer 8 Control/Status Register Message Buffer 8 ID High Register Message Buffer 8 ID Low Register Message Buffer 8 Data Register Message Buffer 8 Data Register Message Buffer 8 Data Register Message Buffer 8 Data Register Reserved FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB9_DATA $88 $89 $8A $8B $8C $8D $8E Message Buffer 9 Control/Status Register Message Buffer 9 ID High Register Message Buffer 9 ID Low Register Message Buffer 9 Data Register Message Buffer 9 Data Register Message Buffer 9 Data Register Message Buffer 9 Data Register Reserved FCMB10_CONTROL FCMB10_ID_HIGH FCMB10_ID_LOW FCMB10_DATA FCMB10_DATA $90 $91 $92 $93 $94 Message Buffer 10 Control/Status Register Message Buffer 10 ID High Register Message Buffer 10 ID Low Register Message Buffer 10 Data Register Message Buffer 10 Data Register
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Table 4-38 FlexCAN Registers Address Map (FC_BASE = $00F800) (Continued)
Register Acronym FCMB10_DATA FCMB10_DATA Address Offset $95 $96 Register Description Message Buffer 10 Data Register Message Buffer 10 Data Register Reserved FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB11_DATA $98 $99 $9A $9B $9C $9D $9E Message Buffer 11 Control/Status Register Message Buffer 11 ID High Register Message Buffer 11 ID Low Register Message Buffer 11 Data Register Message Buffer 11 Data Register Message Buffer 11 Data Register Message Buffer 11 Data Register Reserved FCMB12_CONTROL FCMB12_ID_HIGH FCMB12_ID_LOW FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB12_DATA $A0 $A1 $A2 $A3 $A4 $A5 $A6 Message Buffer 12 Control/Status Register Message Buffer 12 ID High Register Message Buffer 12 ID Low Register Message Buffer 12 Data Register Message Buffer 12 Data Register Message Buffer 12 Data Register Message Buffer 12 Data Register Reserved FCMB13_CONTROL FCMB13_ID_HIGH FCMB13_ID_LOW FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB13_DATA $A8 $A9 $AA $AB $AC $AD $AE Message Buffer 13 Control/Status Register Message Buffer 13 ID High Register Message Buffer 13 ID Low Register Message Buffer 13 Data Register Message Buffer 13 Data Register Message Buffer 13 Data Register Message Buffer 13 Data Register Reserved FCMB14_CONTROL FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB14_DATA $B0 $B1 $B2 $B3 $B4 $B5 $B6 Message Buffer 14 Control/Status Register Message Buffer 14 ID High Register Message Buffer 14 ID Low Register Message Buffer 14 Data Register Message Buffer 14 Data Register Message Buffer 14 Data Register Message Buffer 14 Data Register Reserved
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Table 4-38 FlexCAN Registers Address Map (FC_BASE = $00F800) (Continued)
Register Acronym FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA FCMB15_DATA Address Offset $B8 $B9 $BA $BB $BC $BD $BE Register Description Message Buffer 15 Control/Status Register Message Buffer 15 ID High Register Message Buffer 15 ID Low Register Message Buffer 15 Data Register Message Buffer 15 Data Register Message Buffer 15 Data Register Message Buffer 15 Data Register Reserved
Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs) and to signal to the 56800E core when an interrupt of sufficient priority exists and to what address to jump in order to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features: * Programmable priority levels for each IRQ * Two programmable Fast Interrupts * Notification to SIM module to restart clocks out of Wait and Stop modes * Drives initial address on the address bus after reset For further information, see Table 4-5, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 82 interrupt sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. Within a given priority level, zero is the highest priority, while number 81 is the lowest.
5.3.1
Normal Interrupt Handling
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the vector number to determine the vector address. In this way, an offset is generated into the vector table for each interrupt.
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5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level.
Table 5-1 Interrupt Mask Bit Definition
SR[9]1 0 0 1 1 SR[8]1 0 1 0 1 Permitted Exceptions Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3 Masked Exceptions None Priority 0 Priorities 0, 1 Priorities 0, 1, 2
1. Core status register bits indicating current interrupt mask within the core.
Table 5-2 Interrupt Priority Encoding
IPIC_LEVEL[1:0]1 00 01 10 11 Current Interrupt Priority Level No Interrupt or SWILP Priority 0 Priority 1 Priorities 2 or 3 Required Nested Exception Priority Priorities 0, 1, 2, 3 Priorities 1, 2, 3 Priorities 2, 3 Priority 3
1. See IPIC field definition in Section 5.6.30.2.
5.3.3
Fast Interrupt Handling
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does. A fast interrupt is defined (to the ITCN) by: 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers. 2. Setting the FIMn register to the appropriate vector number. 3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt. When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its fast interrupt handling.
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5.4 Block Diagram
Priority Level any0 Level 0 82 -> 7 Priority Encoder
7
INT1
2 -> 4 Decode
INT VAB CONTROL IPIC
any3 Level 3 Priority Level 82 -> 7 Priority Encoder IACK
7
SR[9:8] PIC_EN
INT82
2 -> 4 Decode
Figure 5-1 Interrupt Controller Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation: * * Functional Mode The ITCN is in this mode by default. Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA and IRQB signals automatically become low-level sensitive in these modes even if the control register bits are set to make them falling-edge sensitive. This is because there is no clock available to detect the falling edge. Peripheral which require a clock to generate interrupts will not be able to generate interrupts during STOP mode. The FlexCAN module can wake the device from STOP, and a reset will do just that, or IRQA and IRQB can wake it up.
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers.
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Register Descriptions
Table 5-3 ITCN Register Summary (ITCN_BASE = $00F1A0)
Register Acronym IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP0 IRQP1 IRQP2 IRQP3 IRQP4 IRQP5 Reserved ICTL Base Address + $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 $16 $17 $1D Interrupt Control Register 5.6.30 Register Name Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Interrupt Priority Register 7 Interrupt Priority Register 8 Interrupt Priority Register 9 Vector Base Address Register Fast Interrupt 0 Match Register Fast Interrupt 0 Vector Address Low Register Fast Interrupt 0 Vector Address High Register Fast Interrupt 1 Match Register Fast Interrupt 1 Vector Address Low Register Fast Interrupt 1 Vector Address High Register IRQ Pending Register 0 IRQ Pending Register 1 IRQ Pending Register 2 IRQ Pending Register 3 IRQ Pending Register 4 IRQ Pending Register 5 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18 5.6.19 5.6.20 5.6.21 5.6.22 5.6.23
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Add. Register Offset Name $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F $10 $11 $12 $13 $14 $15 IPR0 IPR1 IPR2 IPR3 IPR4 IPR5 IPR6 IPR7 IPR8 IPR9 VBA R W R W R W R W R
15
0 0
14
0 0
13
12
11
10
9
0 0
8
0 0
7
0 0
6
0 0
5
0
4
0
3
0
2
0
1
0
0
0
BKPT_U0 IPL 0 0
STPCNT IPL 0 0
RX_REG IPL 0 0
TX_REG IPL IRQB IPL FCBOFF IPL GPIOB IPL SCI1_XMIT IPL
TRBUF IPL IRQA IPL 0 0
FMCBE IPL GPIOD IPL SPI0_RCV IPL
FMCC IPL GPIOE IPL SPI1_XMIT IPL
FMERR IPL GPIOF IPL SPI1_RCV IPL SCI1_RCV IPL TMRD2 IPL TMRB2 IPL 0 0 0 0
LOCK IPL FCMSGBUF IPL 0 0
LVI IPL FCWKUP IPL 0 0 0 0
FCERR IPL GPIOA IPL SCI1_TIDL IPL 0 0
W R DEC1_XIRQ IPL DEC1_HIRQ IPL W R TMRC0 IPL TMRD3 IPL W R W R SCI0_RCV IPL SCI0_RERR IPL W SCI0_RCV IPL SCI0_RERR IPL R PWMA F IPL PWMB F IPL W 0 0 0 R
0 0 0 0 TMRA0 IPL TMRB3 IPL
GPIOC IPL SPI0_XMIT IPL
SCI1_RERR IPL TMRD1 IPL TMRB1 IPL SCI0_TIDL IPL SCI0_TIDL IPL PWMB_RL IPL
TMRD0 IPL TMRB0 IPL SCI0_XMIT IPL SCI0_XMIT IPL ADCA_ZC IPL
DEC0_XIRQ IPL DEC0_HIRQ IPL TMRC2 IPL TMRA2 IPL TMRA2 IPL ADCA_CC IPL TMRC1 IPL TMRA1 IPL TMRA1 IPL ADCB_CC IPL
TMRC3 IPL TMRA3 IPL TMRA3 IPL ABCB_ZC IPL
PWMA_RL IPL
VECTOR BASE ADDRESS 0 0 0 0 0
W R VBA0 W R FIVAL0 W R FIVAH0 W R FIM1 W R FIVAL1 W R FIVAH1 W R IRQP0 W R IRQP1 W R IRQP2 W R IRQP3 W R IRQP4 W IRQP5 Reserved Reserved Reserved Reserved Reserved Reserved ICTL R W R W R W
FAST INTERRUPT 0
FAST INTERRUPT 0 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT 1
FAST INTERRUPT 1 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAST INTERRUPT 1 VECTOR ADDRESS HIGH 1
PENDING [16:2] PENDING [32:17] PENDING [48:33] PENDING [64:49] PENDING [80:65]
$16 $17 $18 $19 $1A $1B $1C $1D
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PENDING [81]
INT
IPIC
VAB
INT_DIS
1
IRQB STATE
IRQA STATE
IRQB EDG
IRQA EDG
0
= Read as 0 = Reserved
Figure 5-2 ITCN Register Map Summary
70 56F8346 Technical Data Preliminary MOTOROLA
Register Descriptions
5.6.1
Base + $0 Read Write RESET
Interrupt Priority Register 0 (IPR0)
15
0
14
0
13
12
11
10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
BKPT_U0 IPL 0 0 0 0
STPCNT IPL 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1 5.6.1.2
Reserved--Bits 15-14 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)-- Bits13-12
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.1.3
EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)-- Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.1.4
Reserved--Bits 9-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2
Base + $1 Read Write RESET
Interrupt Priority Register 1 (IPR1)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
RX_REG IPL 0 0 0 0 0 0 0 0 0 0 0 0
TX_REG IPL 0 0
TRBUF IPL 0 0
Figure 5-4 Interrupt Priority Register 1 (IPR1)
5.6.2.1
Reserved--Bits 15-6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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5.6.2.2
EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)--Bits 5-4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.2.3
EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.2.4
EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)-- Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3
5.6.3
Base + $2 Read
Interrupt Priority Register 2 (IPR2)
15 14 13 12 11 10 9 8 7 6 5
0 FMCBE IPL FMCC IPL 0 0 FMERR IPL 0 0 LOCK IPL 0 0 LVI IPL 0 0 0 0
4
0
3
2
1
0
IRQB IPL 0 0
IRQA IPL 0 0
Write RESET
0 0
Figure 5-5 Interrupt Priority Register 2 (IPR2)
5.6.3.1
Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)--Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * *
72
00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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Register Descriptions
5.6.3.2
Flash Memory Command Complete Priority Level (FMCC IPL)--Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.3
Flash Memory Error Interrupt Priority Level (FMERR IPL)--Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.4
PLL Loss of Lock Interrupt Priority Level (LOCK IPL)--Bits 9-8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.5
Low Voltage Detector Interrupt Priority Level (LVI IPL)--Bits 7-6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.6
Reserved--Bits 5-4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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5.6.3.7
External IRQ B Interrupt Priority Level (IRQB IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.3.8
External IRQ A Interrupt Priority Level (IRQA IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4
Base + $3 Read
Interrupt Priority Register 3 (IPR3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 GPIODIPL GPIOE IPL GPIOFIPL 0 0 0 0 FCMSGBUF IPL 0 0 FCWKUP IPL 0 0 FCERR IPL 0 0 FCBOFF IPL 0 0 0 0
0
0
Write RESET
0 0
Figure 5-6 Interrupt Priority Register 3 (IPR3)
5.6.4.1
GPIO D Interrupt Priority Level (GPIOD IPL)--Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.2
GPIO E Interrupt Priority Level (GPIOE IPL)--Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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5.6.4.3
GPIO F Interrupt Priority Level (GPIOF IPL)--Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2two. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.4
FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)--Bits 9-8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.5
FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)-- Bits 7-6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.6
FlexCAN Error Interrupt Priority Level (FCERR IPL)-- Bits 5-4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.4.7
FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)-- Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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5.6.4.8
Reserved--Bits 1-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5
Base + $4 Read Write RESET
Interrupt Priority Register 4 (IPR4)
15 14 13 12 11 10 9
0
8
0
7
0
6
0
5
4
3
2
1
0
SPI0_RCV IPL 0 0
SPI1_XMIT IPL 0 0
SPI1_RCV IPL 0 0
GPIOA IPL 0 0 0 0 0 0
GPIOB IPL 0 0
GPIOC IPL 0 0
Figure 5-7 Interrupt Priority Register 4 (IPR4)
5.6.5.1
SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)-- Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.2
SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)-- Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.3
SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)-- Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.4
Reserved--Bits 9-6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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Register Descriptions
5.6.5.5
GPIO A Interrupt Priority Level (GPIOA IPL)--Bits 5-4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.6
GPIO B Interrupt Priority Level (GPIOB IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.5.7
GPIO C Interrupt Priority Level (GPIOC IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6
Base + $5 Read Write RESET
Interrupt Priority Register 5 (IPR5)
15 14 13 12 11 10 9 8 7
0
6
0
5
4
3
2
1
0
DEC1_XIRQ IPL 0 0
DEC1_HIRQ IPL 0 0
SCI1_RCV IPL 0 0
SCI1_RERR IPL 0 0
SCI1_TIDL IPL 0 0
SCI1_XMIT IPL 0 0
SPI0_XMIT IPL 0 0
0
0
Figure 5-8 Interrupt Priority Register 5 (IPR5)
5.6.6.1
Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ IPL)--Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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5.6.6.2
Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC1_HIRQ IPL)--Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6.3
SCI 1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)-- Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6.4
SCI 1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)-- Bits 9-8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6.5 5.6.6.6
Reserved--Bits 7-6 SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)-- Bits 5-4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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Register Descriptions
5.6.6.7
SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)-- Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.6.8
SPI 0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)-- Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7
Base + $6 Read
Interrupt Priority Register 6 (IPR6)
15 14 13 12 11 10 9 8 7 6 5
0 TMRC0 IPL TMRD3 IPL 0 0 TMRD2 IPL 0 0 TMRD1 IPL 0 0 TMRD0 IPL 0 0 0 0
4
0
3
2
1
0
Write RESET
0 0
DEC0_XIRQ IPL 0 0
DEC0_HIRQ IPL 0 0
Figure 5-9 Interrupt Priority Register 6 (IPR6)
5.6.7.1
Timer C Channel 0 Interrupt Priority Level (TMRC0 IPL)-- Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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5.6.7.2
Timer D Channel 3 Interrupt Priority Level (TMRD3 IPL)-- Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.3
Timer D Channel 2 Interrupt Priority Level (TMRD2 IPL)-- Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.4
Timer D Channel 1 Interrupt Priority Level (TMRD1 IPL)-- Bits 9-8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.5
Timer D Channel 0 Interrupt Priority Level (TMRD0 IPL)-- Bits 7-6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.6
Reserved--Bits 5-4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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Register Descriptions
5.6.7.7
Quadrature Decoder 0 INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.7.8
Quadrature Decoder 0 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC0_HIRQ IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.8
Base + $7 Read
Interrupt Priority Register 7 (IPR7)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRA0 IPL
TMRB3 IPL 0 0
TMRB2 IPL 0 0
TMRB1 IPL 0 0
TMRB0 IPL 0 0
TMRC3 IPL 0 0
TMRC2 IPL 0 0
TMRC1 IPL 0 0
Write RESET
0 0
Figure 5-10 Interrupt Priority Register (IPR7)
5.6.8.1
Timer A Channel 0 Interrupt Priority Level (TMRA0 IPL)-- Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.8.2
Timer B Channel 3 Interrupt Priority Level (TMRB3 IPL)-- Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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MOTOROLA
5.6.8.3
Timer B Channel 2 Interrupt Priority Level (TMRB2 IPL)-- Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.8.4
Timer B Channel 1 Interrupt Priority Level (TMRB1 IPL)--Bits 9-8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.8.5
Timer B Channel 0 Interrupt Priority Level (TMRB0 IPL)--Bits 7-6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.8.6
Timer C Channel 3 Interrupt Priority Level (TMRC3 IPL)--Bits 5-4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.8.7
Timer C Channel 2 Interrupt Priority Level (TMRC2 IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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Register Descriptions
5.6.8.8
Timer C Channel 1 Interrupt Priority Level (TMRC1 IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9
Base + $8 Read Write RESET
Interrupt Priority Register 8 (IPR8)
15 14 13 12 11
0
10
0
9
8
7
6
5
4
3
2
1
0
SCI0_RCV IPL 0 0
SCI0_RERR IPL 0 0
SCI0_TIDL IPL 0 0
SCI0_XMIT IPL 0 0
TMRA3 IPL 0 0
TMRA2 IPL 0 0
TMRA1 IPL 0 0
0
0
Figure 5-11 Interrupt Priority Register 8 (IPR8)
5.6.9.1
SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)-- Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.2
SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)-- Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.3
Reserved--Bits 11-10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
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5.6.9.4
SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)-- Bits 9-8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.5
SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)-- Bits 7-6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.6
Timer A Channel 3 Interrupt Priority Level (TMRA3 IPL)--Bits 5-4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.7
Timer A Channel 2 Interrupt Priority Level (TMRA2 IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.9.8
Timer A Channel 1 Interrupt Priority Level (TMRA1 IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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Register Descriptions
5.6.10
Base + $9 Read
Interrupt Priority Register 9 (IPR9)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWMA_F IPL
PWMB_F IPL 0 0
Write RESET
0 0
PWMA_RL IPL 0 0
PWM_RL IPL 0 0
ADCA_ZC IPL ABCB_ZC IPL 0 0 0 0
ADCA_CC IPL 0 0
ADCB_CC IPL 0 0
Figure 5-12 Interrupt Priority Register 9 (IPR9)
5.6.10.1
PWM A Fault Interrupt Priority Level (PWMA_F IPL)--Bits 15-14
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.10.2
PWM B Fault Interrupt Priority Level (PWMB_F IPL)--Bits 13-12
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.10.3
Reload PWM A Interrupt Priority Level (PWMA_RL IPL)-- Bits 11-10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.10.4
Reload PWM B Interrupt Priority Level (PWMB_RL IPL)--Bits 9-8
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
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5.6.10.5
ADC A Zero Crossing Interrupt Priority Level (ADCA_ZC IPL)-- Bits 7-6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.10.6
ADC B Zero Crossing Interrupt Priority Level (ADCB_ZC IPL)-- Bits 5-4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.10.7
ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)--Bits 3-2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.10.8
ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)--Bits 1-0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. * * * * 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2
5.6.11
Base + $A Read Write RESET
Vector Base Address Register (VBA)
15
0
14
0
13
0
12
11
10
9
8
7
6
5
4
3
2
1
0
VECTOR BASE ADDRESS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-13 Vector Base Address Register (VBA)
86 56F8346 Technical Data Preliminary MOTOROLA
Register Descriptions
5.6.11.1 5.6.11.2
Reserved--Bits 15-13 Interrupt Vector Base Address (VECTOR BASE ADDRESS)-- Bits 12-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
The contents of this register determine the location of the Vector Address Table. The value in this register is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower eight bits are determined based upon the highest-priority interrupt. They are then appended onto VBA before presenting the full VAB to the 56800E core; see Section 5.3.1 for details.
5.6.12
Base + $B Read Write RESET
Fast Interrupt 0 Match Register (FIM0)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
FAST INTERRUPT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-14 Fast Interrupt 0 Match Register (FIM0)
5.6.12.1 5.6.12.2
Reserved--Bits 15-7 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)--Bits 6-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This value determines which IRQ will be a Fast Interrupt 0. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Section 5.3.3. IRQs used as fast interrupts must be set to priority level two. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest priority level 2 interrupt regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-5.
5.6.13
Base + $C Read
Fast Interrupt 0 Vector Address Low Register (FIVAL0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST INTERRUPT 0 VECTOR ADDRESS LOW
Write RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.6.13.1
Fast Interrupt 0 Vector Address Low (FIVAL0)--Bits 15-0
The lower 16 bits of the vector address used for fast interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
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5.6.14
Base + $D Read Write RESET
Fast Interrupt 0 Vector Address High Register (FIVAH0)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
FAST INTERRUPT 0 VECTOR ADDRESS HIGH 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.6.14.1 5.6.14.2
Reserved--Bits 15-5 Fast Interrupt 0 Vector Address High (FIVAH0)--Bits 4-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.15
Base + $E Read Write RESET
Fast Interrupt 1 Match Register (FIM1)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
FAST INTERRUPT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-17 Fast Interrupt 1 Match Register (FIM1)
5.6.15.1 5.6.15.2
Reserved--Bits 15-7 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)--Bits 6-0
This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.
This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Section 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt regardless of their location in the interrupt table prior to being declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-5.
5.6.16
Base + $F Read Write RESET
Fast Interrupt 1 Vector Address Low Register (FIVAL1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST INTERRUPT 1 VECTOR ADDRESS LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-18 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
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Register Descriptions
5.6.16.1
Fast Interrupt 1 Vector Address Low (FIVAL1)--Bits 15-0
The lower 16 bits of vector address are used for Fast Interrupt 1. This register is combined with FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.17
Base + $10 Read Write RESET
Fast Interrupt 1 Vector Address High Register (FIVAH1)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
FAST INTERRUPT 1 VECTOR ADDRESS HIGH 0 0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.17.1 5.6.17.2
Reserved--Bits 15-5 Fast Interrupt 1 Vector Address High (FIVAH1)--Bits 4-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.18
Base + $11 Read Write RESET
IRQ Pending 0 Register (IRQP0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 PENDING [16:2]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-20 IRQ Pending 0 Register (IRQP0)
5.6.18.1
IRQ Pending (PENDING)--Bits 15-1
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.18.2
Reserved--Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.19
Read Write RESET
IRQ Pending 1 Register (IRQP1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PENDING [32:17]
$Base + $12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-21 IRQ Pending 1 Register (IRQP1)
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5.6.19.1
IRQ Pending (PENDING)--Bits 32-17
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.20
Base + $13 Read Write RESET
IRQ Pending 2 Register (IRQP2)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PENDING [48:33]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-22 IRQ Pending 2 Register (IRQP2)
5.6.20.1
IRQ Pending (PENDING)--Bits 48-33
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.21
Base + $14 Read Write RESET
IRQ Pending 3 Register (IRQP3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PENDING [64:49]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-23 IRQ Pending 3 Register (IRQP3)
5.6.21.1
IRQ Pending (PENDING)--Bits 64-49
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.22
Base + $15 Read Write RESET
IRQ Pending 4 Register (IRQP4)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PENDING [80:65]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-24 IRQ Pending 4 Register (IRQP4)
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Register Descriptions
5.6.22.1
IRQ Pending (PENDING)--Bits 80-65
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.23
Base + $16 Read Write RESET
IRQ Pending 5 Register (IRQP5)
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
PENDING [81]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-25 IRQ Pending Register 5 (IRQP5)
5.6.23.1 5.6.23.2
Reserved--Bits 96-82 IRQ Pending (PENDING)--Bit 81
This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing.
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. * * 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number
5.6.24 5.6.25 5.6.26 5.6.27 5.6.28 5.6.29
Reserved--Base + 17 Reserved--Base + 18 Reserved--Base + 19 Reserved--Base + 1A Reserved--Base + 1B Reserved--Base + 1C
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5.6.30
Base + $1D Read Write RESET
ITCN Control Register (ICTL)
15
INT
14
IPIC
13
12 11 10
9
VAB
8
7
6
5
INT_DIS
4
1
3
IRQB STATE
2
IRQA STATE
1
IRQB EDG 0
0
IRQA EDG 0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
Figure 5-26 ITCN Control Register (ICTL)
5.6.30.1
* *
Interrupt (INT)--Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core. 0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core
5.6.30.2
Interrupt Priority Level (IPIC)--Bits 14-13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: * * * * Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 00 = Required nested exception priority levels are 0, 1, 2, or 3 01 = Required nested exception priority levels are 1, 2, or 3 10 = Required nested exception priority levels are 2 or 3 11 = Required nested exception priority level is 3
5.6.30.3
Vector Number - Vector Address Bus (VAB)--Bits 12-6
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it.
5.6.30.4
* *
Interrupt Disable (INT_DIS)--Bit 5
This bit allows all interrupts to be disabled. 0 = Normal operation (default) 1 = All interrupts disabled
5.6.30.5 5.6.30.6 5.6.30.7
Reserved--Bit 4 IRQB State Pin (IRQB STATE)--Bit 3 IRQA State Pin (IRQA STATE)--Bit 2
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
This read-only bit reflects the state of the external IRQB pin.
This read-only bit reflects the state of the external IRQA pin.
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Resets
5.6.30.8
IRQB Edge Pin (IRQB Edg)--Bit 1
This bit controls whether the external IRQB interrupt is edge or level sensitive. During Stop and Wait modes, it is automatically level sensitive. * * 0 = IRQB interrupt is a low-level sensitive (default) 1 = IRQB interrupt is falling-edge sensitive.
5.6.30.9
IRQA Edge Pin (IRQA Edg)--Bit 0
This bit controls whether the external IRQA interrupt is edge or level sensitive. During Stop and Wait modes, it is automatically level sensitive. * * 0 = IRQA interrupt is a low-level sensitive (default) 1 = IRQA interrupt is falling-edge sensitive.
5.7 Resets
5.7.1 Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released.
5.7.2
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities: Illegal Instruction; SW Interrupt 3; HW Stack Overflow; Misaligned Long Word Access; SW Interrupt 2; SW Interrupt 1; SW Interrupt 0; and SW Interrupt LP. These interrupts are enabled at their fixed priority levels.
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Part 6 System Integration Module (SIM)
6.1 Overview
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system integration module is responsible for the following functions: * * * * * * * Reset sequencing Clock generation & distribution Stop/Wait control Pull-up enables for selected peripherals System status registers Registers for software access to the JTAG ID of the chip Enforcing Flash security
6.2 Features
The SIM has the following features: * * * Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory Power saving clock gating for peripheral Three power modes (Run, Wait, Stop) to control power utilization -- Stop mode shuts down the 56800E core, system clock, peripheral clock, and PLL operation -- Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be done explicitly -- Wait mode shuts down the 56800E core and unnecessary system clock operation -- Run mode supports full part operation * * * * * * * Controls to enable/disable the 56800E core WAIT and STOP instructions Calculates base delay for reset extension based upon POR and RESET values. Reset delay will be either 3 x 32 clocks (phased release of reset) or 2^21 clock cycles. Controls Reset sequencing after reset Software-initiated reset Four 16-bit registers reset only by a Power-On Reset usable for general purpose software control System Control Register Registers for software access to the JTAG ID of the chip
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Operating Modes
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: * Reset Mode, which has two submodes: -- Hardware Reset Mode 56800E Core and all peripherals are reset. This occurs when the internal POR is asserted,the RESET pin is asserted or when the COP timer times out. -- Software Reset Mode Software reset occurs when a 1 is written into the software RESET (SWRST) bit in the SIM Control Register (SIM_CONTROL). This reset mode is identical to the H/W RESET mode except since the EMI_MODE and EXTBOOT pins are ignored at reset, EXTBOOT is ignored, and the state of the mA bit is conserved. * Run Mode This is the primary mode of operation for this device. In this mode, the 56800E controls chip operation. Debug Mode The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals continue to run except the COP and PWMs. COP is disabled and PWM outputs are optionally switched off to disable any motor from being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details. Wait Mode In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped. Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other peripherals continue to run. Stop Mode When in Stop mode, the 56800E core, memory, and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode.
*
*
*
6.4 Operation Mode Register
Bit Type RESET 15
NL R/W 0 0 0 0 0 0 0
14
13
12
11
10
9
8
CM R/W 0
7
XP R/W 0
6
SD R/W 0
5
R R/W 0
4
SA R/W 0
3
EX R/W 0
2
0
1
MB R/W
0
MA R/W 0
0
0
Figure 6-1 OMR
See Section 4.2 for detailed information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. Additional information on the EX bit see Section 4.4. For all other bits see, Section 8.2.1 of the DSP56800E Reference Manual. Note: The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.
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6.5 Register Descriptions
Table 6-1 SIM Registers (SIM_BASE = $00F350)
Address Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR Address Offset Base + $0 Base + $1 Base + $2 Base + $3 Base + $4 Base + $5 Base + $6 Base + $7 Base + $8 Register Name Control Register Reset Status Register Software Control Register 0 Software Control Register 1 Software Control Register 2 Software Control Register 3 Most Significant Half of JTAG ID Least Significant Half of JTAG ID Pull-up Disable Register Reserved SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL Base + $A Base + $B Base + $C Base + $D Base + $E CLKO Select Register GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register 6.5.7 6.5.7 6.5.8 6.5.9 6.5.10 Section Location 6.5.1 6.5.2 6.5.3 6.5.3 6.5.3 6.5.3 6.5.4 6.5.5 6.5.6
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Register Descriptions
Add. Offset $0 $1 $2 $3 $4 $5 $6 $7
Register Name SIM_ CONTROL SIM_ RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 R W R W R W R W R W
15
0 0
14
0 0
13
0 0
12
0 0
11
0 0
10
0 0
9
0 0
8
0 0
7
0 0
6
0 0
5
Once Ebl0 SWR
4
SW Rst
3
2
1
0
stop_disable POR
wait_disable 0 0
COPR EXTR
FIELD FIELD FIELD FIELD 0 0 0 1 PWMA 1 PWMA 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 PWMA 0 1 0 1 0 1 1 0 1 1 1 0 0 0 1
R W SIM_MSH_ R ID W R SIM_LSH_ID W R SIM_PUDR W Reserved
0 0
CAN CAN
$8
EMI_ RESET MODE EMI_ RESET MODE 0 0 0 0 0 0
IRQ IRQ
XBOOT PWMB
0
CTRL CTRL
0
JTAG JTAG
0
0
0
PWMA XBOOT PWMB 0 A23 A23 0 A22 A22 0 A21 A21 0 A20 A20 0
$A $B $C $D $E
SIM_ CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL
R W R W R W R W R W R W
0 0 0
0 0 0
0 0 0
CLKDIS CLKDIS 0 0
CLKOSEL CLKOSEL HOME INDEX PHSB PHA _ALT _ALT _ALT _ALT SPI1 1 SPI0 1 PWM B PWM
EMI 1
ADCB 1
ADCA 1
CAN 1
DEC1 1
DEC0 1
TMRD TMRC TMRB TMRA 1 1 1 1
SCI1 1
SCI0 1
ISAL[23:22]
ISAL[21:6]
0
= Read as 0 = Reserved
Figure 6-2 SIM Register Map Summary
6.5.1
Base + $0 Read Write RESET
SIM Control Register (SIM_CONTROL)
15
0
14
0
13
O
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
Once Ebl0 0
4
SW RST 0
3
2
1
0
stop_disable 0 0
wait_disable 0 0
0
0
0
0
0
0
0
0
0
0
Figure 6-3 SIM Control Register (SIM_CONTROL)
6.5.1.1 6.5.1.2
* *
Reserved--Bits 15-6 OnCE Enable (OnCEEBL)--Bit 5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
0 = OnCE clock to 56800E core enabled when core TAP is enabled 1 = OnCE clock to 56800E core is always enabled
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6.5.1.3 6.5.1.4
* * * *
Software Reset (SWRST)--Bit 4 Stop Disable (STOP_DISABLE)--Bits 3-2
Writing 1 to this field will cause the part to reset.
00 - STOP mode will be entered when the 56800E core executes a STOP instruction 01 - The 56800E STOP instruction will not cause entry into Stop mode; stop_disable can be reprogrammed in the future 10 - The 56800E STOP instruction will not cause entry into Stop mode; stop_disable can then only be changed by resetting the device 11 - Same operation as 10
6.5.1.5
* * * *
Wait Disable (WAIT_DISABLE)--Bits 1-0
00 - WAIT mode will be entered when the 56800E core executes a WAIT instruction 01 - The 56800E WAIT instruction will not cause entry into Wait mode; wait_disable can be reprogrammed in the future 10 - The 56800E WAIT instruction will not cause entry into Wait mode; wait_disable can then only be changed by resetting the device 11 - Same operation as 10
6.5.2
SIM Reset Status Register (SIM_RSTSTS)
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Software should only clear this register.
Base + $1 Read Write RESET
0 0 0 0 0 0 0 0 0 0 0 0
15
0
14
0
13
O
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
SWR
4
COPR
3
EXTR
2
POR
1
0
0
0
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
6.5.2.1 6.5.2.2
Reserved--Bits 15-6 Software Reset (SWR)--Bit 5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SWRST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
6.5.2.3
COP Reset (COPR)--Bit 4
When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
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Register Descriptions
6.5.2.4
External Reset (EXTR)--Bit 3
If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit position will clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external RESET pin being asserted low.
6.5.2.5
Power on Reset (POR)--Bit 2
When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can only be cleared by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On Reset.
6.5.2.6
Reserved--Bits 1-0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.3
SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3)
Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality.
Base + $2 Read
15
14
13
12
11
10
9
8
FIELD
7
6
5
4
3
2
1
0
Write POR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)
6.5.3.1
Software Control Data 1 (FIELD)--Bits 15-0
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by software developers to contain data that will be unaffected by the other reset sources (reset pin, software reset, and COP reset).
6.5.4
Most Significant Half of JTAG ID (SIM_MSH_ID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F4.
Base + $6 Read Write RESET
0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
1
7
1
6
1
5
1
4
1
3
0
2
1
1
0
0
0
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
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6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads $401D.
Base + $7 Read Write RESET
0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1
15
0
14
1
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
1
2
1
1
0
0
1
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See Table 2-2 to identify which pins can deactivate the internal pull-up resistor.
Base + $8 Read Write RESET
0
15
0
14
PWMA1 0
13
CAN 0
12
EMI_ MODE 0
11
RESET 0
10
IRQ 0
9
XBOOT 0
8
7
6
0
5
CTRL
4
0
3
JTAG
2
0
1
0
0
0
PWMB PWMA0 0 0 0
0
0
0
0
0
0
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1 6.5.6.2 6.5.6.3 6.5.6.4 6.5.6.5 6.5.6.6 6.5.6.7
PWMA1 CAN EMI_MODE RESET IRQ XBOOT PWMB
This bit controls the pull-up resistors on the FAULTA3 pin.
This bit controls the pull-up resistors on the CAN_RX pin.
This bit controls the pull-up resistors on the EMI_MODE pin.
This bit controls the pull-up resistors on the RESET pin.
This bit controls the pull-up resistors on the IRQA and IRQB pins.
This bit controls the pull-up resistors on the EXTBOOT pin.
This bit controls the pull-up resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3 pins.
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Register Descriptions
6.5.6.8 6.5.6.9 6.5.6.10
PWMA0 CTRL JTAG
This bit controls the pull-up resistors on the FAULTA0, FAULTA1, and FAULTA2 pins.
This bit controls the pull-up resistors on the WR and RD pins.
This bit controls the pull-up resistors on the TRST, TMS and TDI pins.
6.5.7
CLKO Select Register (SIM_CLKOSR)
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are for test purposes only, and are subject to significant unspecified latencies at high frequencies. The upper four bits of the GPIO B register can function as GPIO, A[23:20], or as additional clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIO B[7:4] are programmed to operate as peripheral outputs, then the choice between A[23:20] and additional clock outputs is done here in the CLKOSR. The default state is for the peripheral function of GPIO B[7:4] to be programmed as A[23:20]. This can be changed by altering A23 through A20 below.
Base + $A Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
A23
8
A22 0
7
A21 0
6
A20 0
5
CLK DIS 1
4
3
2
CLKOSEL
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
6.5.7.1 6.5.7.2
* *
Reserved--Bits 15-10 GPIO B[7] Peripheral Function Select (A23)--Bit 9
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
0 = Peripheral output function of GPIO B[7] is defined to be A[23] 1 = Peripheral output function of GPIO B[7] is defined to be the oscillator clock (MSTR_OSC, see Figure 3-4)
6.5.7.3
* *
GPIO B[6] Peripheral Function Select (A22)--Bit 8
0 = Peripheral output function of GPIO B[6] is defined to be A[22] 1 = Peripheral output function of GPIO B[6] is defined to be SYS_CLK_X2
6.5.7.4
* *
GPIO B[5] Peripheral Function Select (A21)--Bit 7
0 = Peripheral output function of GPIO B[5] is defined to be A[21] 1 = Peripheral output function of GPIO B[5] is defined to be sys_clk
6.5.7.5
* *
GPIO B[4] Peripheral Function Select (A20)--Bit 6
0 = Peripheral output function of GPIO B[4] is defined to be A[20] 1 = Peripheral output function of GPIO B[4] is defined to be the prescaler clock (FREF, see Figure 3-4)
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6.5.7.6
* *
Clockout Disable (CLKDIS)--Bit 5
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL 1 = CLKOUT is tri-stated
6.5.7.7
* * * * * * * * * * * * * * * * * *
CLockout Select (CLKOSEL)--Bits 4-0
Selects clock to be muxed out on the CLKO pin. 00000 = SYS_CLK (from OCCS - DEFAULT) 00001 = Reserved for factory test--56800E clock 00010 = Reserved for factory test--XRAM clock 00011 = Reserved for factory test--PFLASH odd clock 00100 = Reserved for factory test--PFLASH even clock 00101 = Reserved for factory test--BFLASH clock 00110 = Reserved for factory test--DFLASH clock 00111 = Oscillator output 01000 = Fout (from OCCS) 01001 = Reserved for factory test--IPB clock 01010 = Reserved for factory test--Feedback (from OCCS, this is path to PLL) 01011 = Reserved for factory test--Prescaler Clk (from OCCS) 01100 = Reserved for factory test--Postscaler Clk (from OCCS) 01101 = Reserved for factory test--SYS_CLK_x2 (from OCCS) 01110 = Reserved for factory test--SYS_CLK_DIV2 01111 = Reserved for factory test--SYS_CLK_D 10000 = ADCA Clk 10001 = ADCB Clk
6.5.8
GPIO Peripheral Select Register (SIM_GPS)
The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B; these peripherals work together. The four I/O pins associated with GPIO C can function as GPIO, Quad Decoder 1/Quad Timer B or as SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in Figure 6-10 and Table 6-2. When GPIO C[3:0] are programmed to operate as peripheral I/O, then the choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and in conjunction with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function of GPIO C[3:0] to be programmed as decoder functions. This can be changed by altering the appropriate controls in the indicated registers.
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Register Descriptions
GPIOC_PER Register
GPIO Controlled
0 I/O Pad Control 1
SIM_ GPS Register Quad Timer Controlled 0
SPI Controlled
1
Figure 6-10 Overall Control of Pads Using SIM_GPS Control
Table 6-2 Control of Pads Using SIM_GPS Control 1
Control Registers Pin Function Quad Timer SCR register OEN bits GPIOC_PER GPIOC_DTR SIM_GPS Comments
GPIO Input GPIO Output Quad Timer Input/Quad Decoder Input 2 Quad Timer Output / Quad Decoder Input 3 SPI input SPI output
0 0 1
0 1 --
-- -- 0
-- -- 0 See Table 11-1 in the 56F8300 Peripheral User Manual for the definition of the timer inputs based on the Quad Decoder Mode configuration.
1
--
0
1
1 1
-- --
1 1
-- --
See SPI controls for determining the direction of each of the SPI pins.
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is used for each pin. 2. Reset configuration 3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
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Base + $B Read Write RESET
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
C3
2
C2 0
1
C1 0
0
C0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
6.5.8.1 6.5.8.2
* *
Reserved--Bits 15-4 GPIO C3 (C3)--Bit 3
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
This bit selects the alternate function for GPIOC3. 0 = HOME1/TB3 (default - see "Switch Matrix Mode" bits of the Quad Decoder DECCR register) 1 = SS_B1
6.5.8.3
* *
GPIO C2 (C2)--Bit 2
This bit selects the alternate function for GPIOC2. 0 = INDEX1/TB2 (default) 1 = MISO1
6.5.8.4
* *
GPIO C1 (C1)--Bit 1
This bit selects the alternate function for GPIOC1. 0 = PHASEB1/TB1 (default) 1 = MOSI1
6.5.8.5
* *
GPIO C0 (C0)--Bit 0
This bit selects the alternate function for GPIOC0. 0 = PHASEA1/TB0 (default) 1 = SCLK1
6.5.9
Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip.
Base + $C Read
15
EMI
14
13
12
CAN 1
11
10
9
8
7
6
TMRA 1
5
4
3
SPI 1 1
2
SPI 0 1
1
PWMB 1
0
PWMA 1
ADCB ADCA 1 1
DEC1 DEC0 TMRD TMRC TMRB 1 1 1 1 1
SCI 1 SCI 0 1 1
Write RESET
1
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
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6.5.9.1
* *
External Memory Interface Enable (EMI)--Bit 15
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.2
* *
Analog-to-Digital Converter B Enable (ADCB)--Bit 14
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.3
* *
Analog-to-Digital Converter A Enable (ADCA)--Bit 13
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.4
* *
FlexCAN Enable (CAN)--Bit 12
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.5
* *
Decoder 1 Enable (DEC1)--Bit 11
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.6
* *
Decoder 0 Enable (DEC0)--Bit 10
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.7
* *
Quad Timer D Enable (TMRD)--Bit 9
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.8
* *
Quad Timer C Enable (TMRC)--Bit 8
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
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6.5.9.9
* *
Quad Timer B Enable (TMRB)--Bit 7
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.10
* *
Quad Timer A Enable (TMRA)--Bit 6
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.11
* *
Serial Communications Interface 1 Enable (SCI1)--Bit 5
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.12
* *
Serial Communications Interface 0 Enable (SCI0)--Bit 4
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.13
* *
Serial Peripheral Interface 1 Enable (SPI1)--Bit 3
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.14
* *
Serial Peripheral Interface 0 Enable (SPI0)--Bit 2
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.15
* *
Pulse Width Modulator B Enable (PWMB)--1
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.16
* *
Pulse Width Modulator A Enable (PWMA)--0
Each bit controls clocks to the indicated peripheral. 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled)
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6.5.10
I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short address mode. The I/O short address mode allows the instruction to specify the lower six bits of address and the upper address bits are not directly controllable. This register set allows limited control of the full address, as shown in Figure 6-13. Note: If this register is set to something other than the top of memory (EOnCE register space) and the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected. "Hard Coded" Address Portion
Instruction Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_ISALL Register
2 bits from SIM_ISALH Register
Full 24-Bit for Short I/O Address
Figure 6-13 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_ISAL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register to its previous contents prior to returning from interrupt. Note: Note: The default value of this register set points to the EOnCE registers. The pipeline delay between setting this register set and using short I/O addressing with the new value is three cycles.
Base + $D Read Write RESET
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
0
ISAL[23:22] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)
6.5.10.1
Input/Output Short Address Low (ISAL[23:22])--Bit 1-0
This field represents the upper two address bits of the "hard coded" I/O short address.
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Base + $E Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ISAL[21:6]
Write RESET
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL)
6.5.10.2
Input/Output Short Address Low (ISAL[21:6])--Bit 15-0
This field represents the lower 16 address bits of the "hard coded" I/O short address.
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and system (core and memory) clocks. The maximum master clock frequency is 120Mhz. Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60Mhz. The SIM provides power modes (STOP, WAIT) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL) to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible means to manage power consumption. Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may be shut down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused. Clock enables provide the means to disable individual clocks. Some peripherals provide further controls to disable unused sub-functions. Refer to the Part 3 On-Chip Clock Synthesis (OCCS) and the 56F8300 Peripheral User Manual for further details.
6.7 Power-Down Modes Overview
The 56F8346 operates in one of three power-down modes, as shown in Table 6-3.
Table 6-3 Clock Operation in Power-Down Modes
Mode Run Wait Core Clocks Active Core and memory clocks disabled Peripheral Clocks Active Active Description Device is fully functional Peripherals are active and can product interrupts if they have not been masked off. Interrupts will cause the core to come out of its suspended state and resume normal operation. Typically used for power-conscious applications. The only possible recoveries from Stop mode are: 1. CAN traffic (1st message will be lost) 2. Non-clocked interrupts 3. COP reset 4. External reset 5. Power-on reset
Stop
System clocks continue to be generated in the SIM, but most are gated prior to reaching memory, core and peripherals.
All peripherals, except the COP/watchdog timer, run off the IPbus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK = 60MHz.
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Refer to the PCE register in Section 6.5.9 and ADC power modes. Power is a function of the system frequency which can be controlled through the OCCS.
6.8 Stop and Wait Mode Disable Function
Permanent Disable
D D-FLOP
Q
C
56800E
Reprogrammable Disable D D-FLOP Q
STOP_DIS
Clock Select
C
R
RESET
Note: Wait disable circuit is similar
Figure 6-16 Internal Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E system clock must be set equal to the prescaler output. Some applications require the 56800E STOP/WAIT instructions be disabled. To disable those instructions, write to the SIM control register (SIM_CONTROL) described in Section 6.5.1. This procedure can be on either a permanent or temporary basis. Permanently assigned applications last only until their next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external reset pin and the Power-On Reset (POR). The two synchronous sources are the software reset, which is generated within the SIM itself by writting to the SIM_CONTROL register, and the COP reset. Using an 8MHz crystal, the longest reset time is roughly 1/4 second. The first mode is designed to allow sufficient time for the crystal frequency to stabilize before enabling the rest of the chip. In all other cases, the default delays are set to 64 clock cycles. Alternately, an external reset generation chip may be used. Resets may be asserted asynchronously, but they are always released internally on a rising edge of the system clock.
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Part 7 Security Features
The 56F8346 offers security features intended to prevent unauthorized users from reading the contents of the FM array. The 56F8346's Flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the Flash array. However, part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program, as this code would defeat the purpose of security. At the same time, the user may also wish to put a "backdoor" in his program. As an example, the user downloads a security key through the SCI, allowing access to a programming routine that updates parameters stored in another section of the Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the 56F8346 can be secured by programming the security bytes located in the FM configuration field, which occupies a portion of the FM array. These non-volatile bytes will keep the part secured through reset and through power-down of the device. Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state of security. When Flash security mode is enabled in accordance with the method described in the Flash Memory module specification, the 56F8346 will disable external P-space accesses restricting code execution to internal memory, disable EXTBOOT=1 mode, and disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected.
7.2 Flash Access Blocking Mechanisms
The 56F8346 has several operating functional and test modes. Effective Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be compromised and read without explicit user permission. Blocking these are outlined in the next subsections.
7.2.1
Forced Operating Mode Selection
At boot time, the SIM determines in which functional modes the 56F8346 will operate. These are: * Internal Boot Mode * External Boot Mode * Secure Mode When Flash security is enabled as described in the Flash Memory module specification, the 56F8346 will boot in internal boot mode, disable all access to external P-space, and start executing code from the Boot Flash at address 0x02_0000. This security affords protection only to applications in which the 56F8346 operates in internal Flash security mode. Therefore, the security feature cannot be used unless all executing code resides on-chip. When security is enabled, any attempt to override the default internal operating mode by asserting the EXTBOOT pin in conjunction with reset will be ignored.
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7.2.2
Disabling EOnCE Access
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the 56F8346 boots, the chip-level JTAG TAP (Test Access Port) is active and provides the chip's boundary scan capability and access to the ID register. Proper implementation of Flash security requires that no access to the EOnCE port is provided when security is enabled. The 56800E core has an input which disables reading of internal memory via the EOnCE/JTAG. The FM sets this input at reset to a value determined by the contents of the FM security bytes.
7.2.3
Flash LOCKOUT_RECOVERY
If a user inadvertently enables security on the 56F8346, a lockout recovery mechanism is provided which allows the complete erasure of the internal Flash contents, including the configuration field, and thus disables security (the protection register is cleared). This does not compromise security, as the entire contents of the user's secured code stored in Flash are erased before security is disabled on the 56F8346 on the next reset or power-up sequence. To start the lockout recovery sequence, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller's instruction register. The LOCKOUT_RECOVERY instruction has an associated 7-bit Data Register (DR) that is used to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0], is used to control the period of the clock used for timed events in the FM erase algorithm. This register must be set with appropriate values before the lockout sequence can begin. Refer to the JTAG section of the 56F8300 Peripheral User Manual for more details on setting this register value. The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz. The "Writing the FMCLKD Register" section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values.
Flash Memory
system_clk 2 input clock 7 FMCLKD 7 7 DIVIDER
FM_CLKDIV JTAG FM_ERASE
Figure 7-1 JTAG to FM Connection for LOCKOUT_RECOVERY
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Two examples of FM_CLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8 = HFM_CLKDIV[6] = 0. Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz. This translates into an HFM_CLKDIV[6:0] value of $13 or $14, respectively.
150[kHz]
( <
system_clk (2) (DIV + 1)
)<
200[kHz]
EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM input clock 16MHz. Because that is greater than 12.8MHz, PRDIV8 = FM_CLKDIV[6] = 1. Using the following equation yields a DIV value of 9 for a clock of 200kHz, and a DIV value of 10 for a clock of 181kHz. This translates to an FM_CLKDIV[6:0] value of $49 or $4A, respectively.
150[kHz]
( <
system_clk (2)(8) (DIV + 1)
)<
200[kHz]
Once the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. For details, see the JTAG Section in the 56F8300 Peripheral User Manual. Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by asserting TRST) and the 56F8346 (by asserting external chip reset) to return to normal unsecured operation.
7.2.4
Product Analysis
The recommended method of unsecuring a programmed 56F8346 for product analysis of field failures is via the backdoor key access. The customer would need to supply Motorola with the backdoor key and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows backdoor key access must be set. An alternative method for performing analysis on a secured hybrid controller would be to mass-erase and reprogram the Flash with the original code, but modify the security bytes. To insure that a customer does not inadvertently lock himself out of the 56F8346 during programming, it is recommended that he program the backdoor access key first, his application code second, and the security bytes within the FM configuration field last.
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Part 8 General Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip-specific information. Any information contained here supercedes the generic information in the 56F8300 Peripheral User Manual.
8.2 Configuration
There are six GPIO ports defined on the 56F8346. The width of each port and the associated peripheral function is shown in Table 8-1. The specific mapping of GPIO port pins is shown in Table 8-2.
Table 8-1 GPIO Ports Configuration
GPIO Port A B Port Width 14 8 Available Pins in 56F8346 14 1 Peripheral Function Reset Function
14 pins - EMI Address pins 1 pin - EMI Address pin 7 pins - EMI Address pins - Not available in this package 4 pins -DEC1 / TMRB / SPI1 4 pins -DEC0 / TMRA 3 pins -PWMA current sense 2 pins - EMI CSn 4 pins - EMI CSn - Not available in this package 2 pins - SCI1 2 pins - EMI CSn 3 pins -PWMB current sense 2 pins - SCI0 2 pins - EMI Address pins 4 pins - SPI0 1 pin - TMRC 1 pin - TMRC 2 pins - TMRD 2 pins - TMRD 16 pins - EMI Data
EMI Address EMI Address N/A DEC1 / TMRB DEC0 / TMRA PWMA current sense EMI Chip Selects N/A SCI1 EMI Chip Selects PWMB current sense SCI0 EMI Address SPI0 TMRC N/A TMRD N/A EMI Data
C
11
11
D
13
9
E
14
11
F
16
16
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Table 8-2 GPIO External Signals Map
GPIO Port GPIO Bit
0 1 2 3 4 5 6 GPIOA 7 8 9 10 11 12 13 0 1 2 3 GPIOB 4 5 6 7 NA NA NA NA NA NA NA NA Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral GPIO NA NA NA A15 A0 A1 A2 A3 A4 A5 A16 NA NA NA Reset Function Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Functional Signal A8 A9 A10 A11 A12 A13 A14
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Configuration
Table 8-2 GPIO External Signals Map (Continued)
GPIO Port GPIO Bit
0 1 2 3 4 GPIOC 5 6 7 8 9 10 0 1 2 3 4 5 GPIOD 6 7 8 9 10 11 12 Reset Function Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral GPIO GPIO NA NA NA NA Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Functional Signal PhaseA1 / TB0 / SCLK11 PhaseB1 / TB1 / MOSI11 Index1 / TB2 / MISO11 Home1 / TB3 / SS11 PHASEA0 / TA0 PHASEB0 / TA1 Index0 / TA2 Home0 / TA3 ISA0 ISA1 ISA2 CS2 CS3 NA NA NA NA TXD1 RXD1 PS / CS0 DS / CS1 ISB0 ISB1 ISB2
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Table 8-2 GPIO External Signals Map (Continued)
GPIO Port GPIO Bit
0 1 2 3 4 5 6 GPIOE 7 8 9 10 11 12 13 0 1 2 3 4 5 6 7 GPIOF 8 9 10 11 12 13 14 15 Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral D15 D0 D1 D2 D3 D4 D5 D6 Peripheral Peripheral NA Peripheral Peripheral NA NA Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral SS0 TC0 NA TD0 TD1 NA NA D7 D8 D9 D10 D11 D12 D13 D14 Reset Function Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Functional Signal TXD0 RXD0 A6 A7 SCLK0 MOSI0 MISO0
1. See Section 6.5.8 to determine how to select peripherals from this set; DEC1 is the selected peripheral at reset .
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Memory Maps
8.3 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and GPIOx_PER registers change from chip to chip. Tables 4-29 through 4-34 define the actual reset values of these registers for the 56F8346.
Part 9 Joint Test Action Group (JTAG)
9.1 56F8346 Information
Please contact your Motorola marketing representative for device/package-specific BSDL information.
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Part 10 Specifications
10.1 General Characteristics
The 56F8346 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term "5V-tolerant" refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage. Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Note: All specification meet both Automotive and Industrial requirements unless individual specifications are listed.
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
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General Characteristics
Table 10-1 Absolute Maximum Ratings
(VSS = VSSA_ADC = 0) Characteristic Supply voltage ADC Supply Voltage Symbol VDD_IO VDDA_ADC, VREFH VDDA_OSC_PLL VDDA_CORE VIN VINA VOUT VOD TA TA TJ TJ TSTG TSTG
OCR_DIS is High Pin Groups 1, 2, 5, 6, 9, 10, 14 Pin Groups 11, 12, 13 Pin Groups 1, 2, 3, 4, 5, 6, 7, 8 Pin Groups 4, 14
Notes
Min - 0.3
Max 4.0 4.0
Unit V V
VREFH must be
less than or equal to VDDA_ADC
- 0.3
Oscillator/PLL Supply Voltage Internal Logic Core Supply Voltage Input Voltage (digital) Input Voltage (analog) Output Voltage Output Voltage (open drain) Ambient Temperature (Automotive) Ambient Temperature (Industrial) Junction Temperature (Automotive) Junction Temperature (Industrial) Storage Temperature (Automotive) Storage Temperature (Industrial)
- 0.3 - 0.3 -0.3 -0.3 -0.3 -0.3 -40 -40 -40 -40 -55 -55
4.0 3.0 6.0 4.0 4.0 6.0 125 105 150 125 150 150
V V V V V V C C C C C C
Pin Group 1: TXD0-1, RXD0-1, SS0, MISO0, MOSI0 Pin Group 2: PHASEA0-1, PHASEB0-1, INDEX0-1, HOME0-1, ISB0-2, RSTO, ISA0-2, TC0, SCLK0 Pin Group 3: RSTO, TDO Pin Group 4: CAN_TX Pin Group 5: A0-5, D0-15, GPIOD0-1, PS, DS Pin Group 6: A6-15, GPIOB0, TD0-1 Pin Group 7: CLKO, WR, RD
Pin Group 8: PWMA0-5, PWMB0-5 Pin Group 9: IRQA, IRQB, RESET, EXTBOOT, TRST, TMS, TDI, CAN_RX, EMI_MODE, FAULTA0-3, FAULTB0-3 Pin Group 10: TCK Pin Group 11: XTAL, EXTAL Pin Group 12: ANA0-7, ANB0-7 Pin Group 13: OCR_DIS, CLKMODE Pin Group 14: DE
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Although the 56F8346 is specified to operate correctly over the full -40C to 125C ambient temperature range, it is assumed not to be at the extremes of this range 100% of the time.
Table 10-2 Junction Temperature Profile
Temperature 40C 80C 110C 125C 150C Total Hours of Operation 99,000 27,000 5,400 2,700 900 135,000
Table 10-3 Electrostatic Discharge Protection
Characteristic ESD for Human Body Model (HBM) ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Min 2000 200 500 Typ -- -- -- Max -- -- -- Unit V V V
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General Characteristics
Table 10-4 Thermal Characteristics6
Value Characteristic
Comments
Symbol 128-pin LQFP
Unit
Notes
Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection Junction to ambient (@1m/sec) Four layer board (2s2p) Four layer board (2s2p)
RJA RJMA RJMA (2s2p) RJMA RJC JT P I/O PD PDMAX
50.8
C/W
2
46.5 43.9
C/W C/W
2 1,2
41.7
C/W
1,2
Junction to case Junction to center of case I/O pin power dissipation Power dissipation Junction to center of case
13.9 1.2 User Determined P D = (IDD x VDD + P I/O) (TJ - TA) /JA
C/W C/W W W C
3 4
Notes: 1. 2. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. Junction to ambient thermal resistance, Theta-JA (RJA) was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p where "s" is the number of signal layers and "p" is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. Junction to case thermal resistance, Theta-JC (RJC ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. Thermal Characterization Parameter, Psi-JT (JT ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in JESD51-2. JT is a useful value to use to estimate junction temperature in steady state customer environments. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. See Section 12.1 for more details on thermal design considerations.
3.
4.
5. 6.
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Table 10-5 Recommended Operating Conditions
(VREFLO= 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL )
Characteristic Supply voltage ADC Supply Voltage Symbol
VDD_IO VDDA_ADC, VREFH VDDA_OSC
_PLL
Notes
Min 3
Typ 3.3 3.3
Max 3.6 3.6
Unit
V V
VREFH must be less than or equal to VDDA_ADC
3
Oscillator/PLL Supply Voltage Internal Logic Core Supply Voltage Device Clock Frequency Input High Voltage (digital) Input High Voltage (analog) Input High Voltage (XTAL/EXTAL,
XTAL is not driven by an external clock)
3
OCR_DIS is High
3.3 2.5 -- -- -- --
3.6 2.75 60 5.5 VDDA+0.3 VDDA+0.3
V V MHz V V V
VDD_CORE FSYSCLK VIN VIHA VIHC
2.25 0
Pin Groups 1, 2, 5, 6, 9, 10, 14 Pin Group13 Pin Group11
2 2 VDDA-0.8
Input high voltage (XTAL/EXTAL,
XTAL is driven by an external clock)
VIHC VIL
Pin Group 11 Pin Groups 1, 2, 5, 6, 9, 10, 11, 13, 14 Pin Groups 1,2,3 Pin Groups 5,6,7 Pin Groups 8
2 -0.3
-- --
VDDA+0.3 0.8
V V
Input Low Voltage
Output High Source Current1 VOH = 2.4V (VOH min.) Output Low Sink Current1 VOL = 0.4V (VOL max)
IOH
-- -- -- -- -- -- -40 -40 -- -- -- -- --
-4 -8 -12 4 8 12
125 (RJA X PD) 105 (RJA X PD)
mA
IOL
Pin Groups 1,2,3,4,14 Pin Groups 5,6,7 Pin Groups 8
mA
Ambient Operating Temperature (Automotive) Ambient Operating Temperature (Industrial) Flash Endurance (Automotive) (Program Erase Cycles) Flash Endurance (Industrial) (Program Erase Cycles) Flash Data Retention
TA TA NF NF TR
TA = -40C to 125C TA = -40C to 105C TJ <= 70C avg
C C Cycles Cycles Years
10,000 10,000 15
-- -- --
Note 1. Total chip source or sink current cannot exceed 200 mA
Pin Group 1: TXD0-1, RXD0-1, SS0, MISO0, MOSI0 Pin Group 2: PHASEA0-1, PHASEB0-1, INDEX0-1, HOME0-1, ISB0-2, RSTO, ISA0-2, TC0, SCLK0 Pin Group 3: RSTO, TDO Pin Group 4: CAN_TX Pin Group 5: A0-5, D0-15, GPIOD0-1, PS, DS Pin Group 6: A6-15, GPIOB0, TD0-1 Pin Group 7: CLKO, WR, RD Pin Group 8: PWMA0-5, PWMB0-5 Pin Group 9: IRQA, IRQB, RESET, EXTBOOT, TRST, TMS, TDI, CAN_RX, EMI_MODE, FAULTA0-3, FAULTB0-3 Pin Group 10: TCK Pin Group 11: XTAL, EXTAL Pin Group 12: ANA0-7, ANB0-7 Pin Group 13: OCR_DIS, CLKMODE Pin Group 14: DE
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DC Electrical Characteristics
10.2 DC Electrical Characteristics
Table 10-6 DC Electrical Characteristics
Over Recommended Operating Conditions, VDDA = VDDA_ADC,_VDDA_OSC_PLL Characteristic Output High Voltage Output Low Voltage Digital Input Current High
pull-up enabled or disabled
Symbol
VOH VOL IIH IIH IIHA IIHADC IIL IIL IIL IILA IILADC IEXTAL IXTAL
Notes
Min 2.4 --
Typ -- -- 0 80 0 0 -100 0 0 0 0 0 0 -- 0
Max -- 0.4 +/- 2.5 160 +/- 2.5 +/- 3.5 -200 +/- 2.5 +/- 2.5 +/- 2.5 +/- 3.5 +/- 2.5 +/- 2.5 200 +/- 2.5
Unit
V V
A A A A A A A A A A A A A
Test Conditions
IOH =IOHmax IOL =IOLmax VIN = 3.0V to 5.5V VIN = 3.0V to 5.5V VIN = VDDA VIN = VDDA VIN = 0V VIN = 0V VIN = 0V VIN = 0V VIN = 0V VIN = VDDA or 0V VIN = VDDA or 0V VIN = VDDA or 0V VOUT = 3.0V to 5.5V or 0V
Pin Groups 1, 2, 5, 6, 9 Pin Group10
-- 40 -- -- -50 -- -- -- -- --
Digital Input Current High
with pull-down
Analog Input Current High ADC Input Current High Digital Input Current Low
pull-up enabled
Pin Group13 Pin Group12 Pin Groups 1,2,5,6,9 Pin Groups 1,2,5,6,9 Pin Group10
Digital Input Current Low
pull-up disabled
Digital Input Current Low
with pull-down
Analog Input Current Low ADC Input Current Low EXTAL Input Current Low
clock input
Pin Group13 Pin Group12
XTAL Input Current Low
clock input
CKLMODE = High CKLMODE = Low
-- -- --
Output Current High Impedance State Schmitt Trigger Input Hysteresis Input Capacitance (EXTAL/XTAL) Output Capacitance (EXTAL/XTAL) Input Capacitance Output Capacitance See Pin Groups in Table 10-5
IOZ
Pin Groups 1, 2, 3, 4, 5, 6, 7, 8,14 Pin Groups 2, 6, 9,10
VHYS CINC COUTC CIN COUT
-- -- -- -- --
0.3 4.5 5.5 6 6
-- -- -- -- --
V
pF
pF
pF pF
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Table 10-7 Power on Reset Low Voltage Parameters
Characteristic POR Trip Point LVI, 2.5 volt Supply, trip point1 LVI, 3.3 volt supply, trip point2 Bias Current Symbol POR VEI2.5 VEI3.3 Min 1.75 2.05 2.6 Typ 1.8 2.14 2.7 110 Max 1.9 2.25 2.8 130 Units V V V uA
I bias
1. When VDD drops below VEI2.5, an interrupt is generated. 2. When VDD drops below VEI3.3, an interrupt is generated.
Table 10-8 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Enabled (OCR_DIS = Low)
Mode RUN1_MAC IDD_IO1 125mA IDD_ADC 50mA IDD_OSC_PLL 2.5mA Test Conditions * 60MHz Device Clock * All peripheral clocks are enabled * Continuous MAC instructions with fetches from Data RAM * ADC powered on and clocked Wait3 73mA 0uA 2.5mA * 60MHz Device Clock * All peripheral clocks are enabled * ADC powered off Stop1 5mA 0uA 200uA * 8MHz Device Clock * All peripheral clocks are off * ADC powered off * PLL powered off Stop2 5mA 0uA 150uA * External Clock is off * All peripheral clocks are off * ADC powered off * PLL powered off
1. No Output Switching
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DC Electrical Characteristics
Table 10-9 Current Consumption per Power Supply Pin (Typical)
On-Chip Regulator Disabled (OCR_DIS = High)
Mode RUN1_MAC IDD_Core 120 mA IDD_IO1 13A IDD_ADC 50mA IDD_OSC_PLL 2.5mA Test Conditions * 60MHz Device Clock * All peripheral clocks are enabled * Continuous MAC instructions with fetches from Data RAM * ADC powered on and clocked Wait3 68mA 13A 0A 2.5mA * 60MHz Device Clock * All peripheral clocks are enabled * ADC powered off Stop1 500A 13uA 0A 200uA * 8MHz Device Clock * All peripheral clocks are off * ADC powered off * PLL powered off Stop2 100A 13A 0A 150A * External Clock is off * All peripheral clocks are off * ADC powered off * PLL powered off
1. No Output Switching
Table 10-10. Regulator Parameters
Characteristic Unloaded Output Voltage (0mA Load) Loaded Output Voltage (250mA load) Line Regulation @ 250mA load (VDD33 ranges from 3.0V to 3.6V) Short Circuit Current ( output shorted to ground) Bias Current Power-down Current Short-Circuit Tollerance (output shorted to ground) Symbol VRNL VRL VR Iss I bias Ipd TRSC Min 2.25 2.25 2.25 -- -- -- 30 Typical -- -- -- -- 5.8 0 -- Max 2.75 2.75 2.75 700 7 2 -- Unit V V V mA mA A minutes
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Table 10-11. PLL Parameters
Characteristics PLL Startup time Resonator Startup time Min-Max Period Variation Peak-to-Peak Jitter Bias Current Quiescent Current, power-down mode Symbol TPS TRS TPV TPJ IBIAS IPD Min 0.3 0.1 120 -- -- -- Typical 0.5 0.18 -- -- 1.5 100 Max 10 1 200 175 2 150 Unit ms ms ps ps mA A
Table 10-12 Temperature Sense Parametrics
Characteristics K-factor1 Supply Voltage Supply Current - OFF Supply Current - ON Accuracy Resolution Symbol K VDDA IDD-OFF IDD-ON TACC RES Min 7 3.0 -- -- -2 -- Typical 7.2 3.3 -- -- -- -- Max -- 3.6 10 250 +2 1 Unit mV/C V A A C C / bit2
1. This is the inverse of the parameter "m" in Figure 14-1 of the 56F8300 Peripheral User Manual. 2. Assuming a 10-bit range from 0V to 3.6V.
10.3 AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 10-6. Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 10-1.
VIH Input Signal Midpoint1 Fall Time
Note: The midpoint is VIL + (VIH - VIL)/2.
Low
High
90% 50% 10%
VIL
Rise Time
Figure 10-1 Input Signal Measurement References
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Flash Memory Characteristics
Figure 10-2 shows the definitions of the following signal states: * * * * Active state, when a bus or signal is driven, and enters a low impedance state Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tri-stated Data Active Data3 Valid Data3
Figure 10-2 Signal States
10.4 Flash Memory Characteristics
Table 10-13 Flash Timing Parameters
Characteristic Program time 1, 2 Erase time3, 4 Mass erase time5 Symbol Min 20 20 100 Typ -- -- -- Max -- -- -- Unit us ms ms
Tprog Terase Tme
1. Program specification guaranteed from TA = 0C to 85C 2. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual for details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Program Flash Module, as it contains two interleaved memories. 3. Erase specification guaranteed from TA = 0C to 85C 4. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash Module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes. 5. Mass erase specification guaranteed from TA = 0C to 85C
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10.5 External Clock Operation Timing
Table 10-14 External Clock Operation Timing Requirements1
Characteristic Frequency of operation (external clock driver)2 Clock Pulse Width3 External clock input rise time4 External clock input fall time5
1. Parameters listed are guaranteed by design. 2. See Figure 10-3 for details on using the recommended connection of an external clock driver. 3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function. 4. External clock input rise time is measured from 10% to 90%. 5. External clock input fall time is measured from 90% to 10%.
Symbol fosc tPW trise tfall
Min 0 2.0 -- --
Typ -- -- -- --
Max 240 -- 10 10
Unit MHz ns ns ns
VIH
External Clock
90% 50% 10%
90% 50% 10%
tPW
tPW
tfall
trise
VIL
Note: The midpoint is VIL + (VIH - VIL)/2.
Figure 10-3 External Clock Timing
10.6 Phase Locked Loop Timing
Table 10-15 PLL Timing
Characteristic External reference crystal frequency for the PLL1 PLL output frequency2 (fOUT/2) PLL stabilization time3 0 to +85C Symbol fosc fop tplls Min 4 160 -- Typ 8 -- 1 Max 8 260 10 Unit MHz MHz ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (fOUT)/2, please refer to the OCCS chapter in the 56F8300 Peripheral User Manual. 3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
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Crystal Oscillator Timing
10.7 Crystal Oscillator Timing
Table 10-16 Crystal Oscillator Parameters
Characteristic Crystal Startup time Resonator Startup time Crystal ESR Crystal Peak-to-Peak Jitter Crystal Min-Max Period Variation Resonator Peak-to-Peak Jitter Resonator Min-Max Period Variation Bias Current, high-drive mode Bias Current, low-drive mode Quiescent Current, power-down mode Symbol TCS TRS RESR TD TPV TRJ TRP IBIASH IBIASL IPD Min 4 0.1 -- 70 0.12 -- -- -- -- -- Typ 5 0.18 -- -- -- -- -- 250 80 0 Max 10 1 120 250 1.5 300 300 290 110 1 Unit ms ms ohms ps ns ps ps A A A
10.8 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices. Figure 10-4 shows sample timing and parameters that are detailed in Table 10-17. The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user controlled wait states. The equation: t = D + P * (M + W) should be used to determine the actual time of each parameter. The terms in the above equation are defined as: t D P M W parameter delay time fixed portion of the delay, due to on-chip path delays. the period of the system clock, which determines the execution rate of the part (i.e. when the device is operating at 120 MHz, P = 8.33 ns). Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible clock duty cycle derating. the sum of the applicable wait state controls. See the "Wait State Controls" column of Table 10-17 for the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for details of what each wait state field controls. = 0.0 all other cases ie. if XTAL duty cycle is 60%, use 0.6
DCA = 0.5 - (XTAL duty cycles), if ZSRC selects prescale clock and prescaler set to / 1.
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Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change if the operating frequency of the part changes. The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain two sets of numbers to account for this difference. The "Wait States Configuration" column of Table 10-17 should be used to make the appropriate selection.
A0-Axx,CS tRD tARDD tARDA RD tAWR tWRWR WR tWR tWAC tWRRD tRDWR tRDA tRDRD
tDWR tDOS D0-D15
tDOH tAD
tRDD tDRD
Data Out
Data In
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 10-4 External Memory Interface Timing
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External Memory Interface Timing
Table 10-17 External Memory Interface Timing
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98 V, VDDIO = VDDA = 3.0-3.6V, TA = -40 to +120C, CL 50pF, P = 8.333ns
Characteristic
Address Valid to WR Asserted
Symbol
tAWR tWR
Wait States Configuration
WWS=0 WWS>0 WWS=0 WWS>0 WWS=0
D
TBD TBD TBD TBD TBD TBD TBD TBD TBD -2.051 -8.995 TBD TBD TBD TBD TBD -14.798 -19.661 TBD TBD TBD TBD TBD2
M
TBD TBD TBD TBD TBD TBD TBD TBD TBD 0.5 + DCA 0.5 TBD TBD TBD N/A1 TBD 1.00 1.25 + DCA TBD TBD TBD TBD TBD TBD TBD TBD TBD
Wait States Controls
WWSS
Unit
ns
WR Width Asserted to WR Deasserted Data Out Valid to WR Asserted
WWS
ns
tDWR
WWS=0 WWS>0 WWS>0
WWSS
ns
Valid Data Out Hold Time after WR Deasserted Valid Data Out Set Up Time to WR Deasserted Valid Address after WR Deasserted RD Deasserted to Address Invalid Address Valid to RD Deasserted Valid Input Data Hold after RD Deasserted RD Assertion Width Address Valid to Input Data Valid
tDOH tDOS tWAC tRDA tARDD tDRD tRD tAD tARDA tRDD tWRRD tRDRD tWRWR tRDWR WWS=0 WWS>0
WWSH
ns
WWS,WWSS WWSH RWSH RWSS,RWS -- RWS RWSS,RWS RWSS RWSS,RWS WWSH,RWSS RWSS,RWSH MDAR,BMDAR WWSS, WWSH MDAR, BMDAR, RWSH, WWSS
ns
ns ns ns ns ns ns
Address Valid to RD Asserted RD Asserted to Input Data Valid
ns ns ns ns ns
WR Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted
TBD TBD TBD TBD
RD Deasserted to WR Asserted
1. 2.
ns
N/A since device captures data before it deasserts RD If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used.
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10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 10-18 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration RESET Deassertion to First External Address Output3 Edge-sensitive Interrupt Request Width IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State4 IRQA Width Assertion to Recover from Stop State5 Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) from external memory Symbol tRAZ tRA tRDA Typical Min -- Typical Max 21 Unit ns See Figure 10-5
16T 63T
-- 64T
ns ns
10-5 10-5
tIRW tIDM tIDM - FAST tIG tIG - FAST tIRI tIRI -FAST tIW
1.5T TBD TBD TBD TBD TBD TBD 1.5T
-- TBD TBD TBD TBD TBD TBD --
ns ns
10-6 10-7
ns
10-7
ns
10-8
ns
10-9
tIF tIF - FAST
-- --
TBD TBD
ns
10-9
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop modes), T = 125ns. 2. Parameters listed are guaranteed by design. 3. During Power-On Reset, it is possible to use the 56F8346 internal reset stretching circuitry to extend this period to 221T. 4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 5. The interrupt instruction fetch is visible on the pins only in Mode 3.
RESET tRA
tRAZ
tRDA
A0-A15, D0-D15
First Fetch
Figure 10-5 Asynchronous Reset Timing
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
IRQA, IRQB
tIRW
Figure 10-6 External Interrupt Timing (Negative-Edge-Sensitive)
A0-A15, First Interrupt Instruction Execution
tIDM IRQA, IRQB
a) First Interrupt Instruction Execution General Purpose I/O Pin
tIG IRQA, IRQB
b) General Purpose I/O
Figure 10-7 External Level-Sensitive Interrupt Timing
IRQA, IRQB
tIRI
A0-A15,
First Interrupt Vector Instruction Fetch
Figure 10-8 Interrupt from Wait State Timing
tIW
IRQA
tIF
A0-A15,
First Instruction Fetch Not IRQA Interrupt Vector
Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing
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10.10 Serial Peripheral Interface (SPI) Timing
Table 10-19 SPI Timing1
Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data set-up time required for inputs Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave
1. Parameters listed are guaranteed by design.
Symbol tC
Min
Max
Unit
See Figure 10-10, 10-11, 10-12, 10-13
50 50 tELD -- 25 tELG -- 100 tCH 17.6 25 tCL 24.1 25 tDS 20 0 tDH 0 2 tA 4.8
-- --
ns ns
10-13 -- -- ns ns 10-13 -- -- ns ns 10-10, 10-11, 10-12, 10-13
-- --
ns ns
10-13 -- -- ns ns 10-10, 10-11, 10-12, 10-13
-- --
ns ns
-- --
ns ns
10-10, 10-11, 10-12, 10-13
10-13 15 ns
tD 3.7 tDV -- -- tDI 0 0 tR -- -- tF -- -- 9.7 9.0 ns ns 11.5 10.0 ns ns -- -- ns ns 4.5 20.4 ns ns 15.2 ns
10-13
10-10, 10-11, 10-12, 10-13
10-10, 10-11, 10-12
10-10, 10-11, 10-12, 10-13
10-10, 10-11, 10-12, 10-13
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Serial Peripheral Interface (SPI) Timing
SS
(Input)
SS is held High on master
tC tR tCL tCH tF tR tF
SCLK (CPOL = 0) (Output)
SCLK (CPOL = 1) (Output)
tDH tDS
tCL
tCH
MISO (Input)
MSB in
tDI
Bits 14-1
tDV
LSB in
tDI(ref)
MOSI (Output)
Master MSB out
tF
Bits 14-1
Master LSB out
tR
Figure 10-10 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC tCL tF tR
SCLK (CPOL = 0) (Output)
tCH
tF
SCLK (CPOL = 1) (Output)
tCL tCH tR tDS tDH
MISO (Input)
tDV(ref)
MSB in
tDI
Bits 14-1
tDV
LSB in
tDI(ref)
MOSI (Output)
Master MSB out
tF
Bits 14- 1
Master LSB out
tR
Figure 10-11 SPI Master Timing (CPHA = 1)
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SS
(Input)
tC tCL tF tR tELG
SCLK (CPOL = 0) (Input)
tELD
tCH tCL
SCLK (CPOL = 1) (Input)
tA tCH tR tF tD
MISO (Output)
tDS
Slave MSB out
Bits 14-1
tDV tDH
Slave LSB out
tDI tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 10-12 SPI Slave Timing (CPHA = 0)
SS
(Input)
tC tF tCL tCH tELD tCL tR
SCLK (CPOL = 0) (Input)
tELG
SCLK (CPOL = 1) (Input)
tDV tA
tCH tF
tR tD
MISO (Output)
tDS
Slave MSB out
Bits 14-1
tDV tDH
Slave LSB out
tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 10-13 SPI Slave Timing (CPHA = 1)
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Quad Timer Timing
10.11 Quad Timer Timing
Table 10-20 Timer Timing1, 2
Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period Symbol PIN PINHL POUT POUTHL Min 2T + 6 1T + 3 1T - 3 0.5T - 3 Max -- -- -- -- Unit ns ns ns ns See Figure 10-14 10-14 10-14 10-14
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design.
Timer Inputs
PIN PINHL PINHL
Timer Outputs
POUT POUTHL POUTHL
Figure 10-14 Timer Timing
10.12 Quadrature Decoder Timing
Table 10-21 Quadrature Decoder Timing1, 2
Characteristic Quadrature input period Quadrature input high/low period Quadrature phase period Symbol PIN PHL PPH Min 4T + 12 2T + 6 1T + 3 Max -- -- -- Unit ns ns ns See Figure 10-15 10-15 10-15
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns. 2. Parameters listed are guaranteed by design.
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PPH
PPH
PPH
PPH
Phase A (Input)
PHL PIN PHL
Phase B (Input)
PHL PIN PHL
Figure 10-15 Quadrature Decoder Timing
10.13 Serial Communication Interface (SCI) Timing
Table 10-22 SCI Timing1
Characteristic Baud Rate2 RXD3 Pulse Width TXD4 Pulse Width Symbol BR RXDPW TXDPW Min Max (fMAX/16) 1.04/BR 1.04/BR Unit Mbps ns ns See Figure
--
0.965/BR 0.965/BR
--
10-16 10-17
1. Parameters listed are guaranteed by design. 2. fMAX is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8346 device. 3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
RXD SCI receive data pin (Input)
RXDPW
Figure 10-16 RXD Pulse Width
TXD SCI receive data pin (Input)
TXDPW
Figure 10-17 TXD Pulse Width
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Controller Area Network (CAN) Timing
10.14 Controller Area Network (CAN) Timing
Table 10-23 CAN Timing1
Characteristic Baud Rate Bus Wake Up detection Symbol BRCAN T WAKEUP Min Max 1 Unit Mbps s See Figure
--
5
--
10-18
--
1. Parameters listed are guaranteed by design
CAN_RX CAN receive data pin (Input)
T WAKEUP
Figure 10-18 Bus Wake Up Detection
10.15 JTAG Timing
Table 10-24 JTAG Timing
Characteristic TCK frequency of operation1 TCK clock pulse width TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time DE assertion time Symbol fOP tPW tDS tDH tDV tTS tTRST tDE Min DC 50 5 5 -- -- 2T2 2T Max sys_clk/8 -- -- -- 30 30 -- -- Unit MHz ns ns ns ns ns ns ns See Figure 10-19 10-19 10-20 10-20 10-20 10-20 10-21 10-22
1. TCK frequency of operation must be less than 1/8 the processor rate. 2. T = processor clock period (nominally 1/60MHz)
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1/fOP tPW
VIH
tPW
VM
TCK (Input) VM = VIL + (VIH - VIL)/2
VM VIL
Figure 10-19 Test Clock Input Timing Diagram
TCK (Input)
tDS tDH
TDI TMS (Input) TDO (Output)
Input Data Valid
tDV
Output Data Valid
tTS
TDO (Output)
tDV
TDO (Output)
Output Data Valid
Figure 10-20 Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 10-21 TRST Timing Diagram
DE tDE
Figure 10-22 EOnCE - Debug Event
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Analog-to-Digital Converter (ADC) Parameters
10.16 Analog-to-Digital Converter (ADC) Parameters
Table 10-25 ADC Parameters
Characteristic Input voltages Resolution Integral Non-Linearity 1 Differential Non-Linearity Monotonicity ADC internal clock Conversion range ADC channel power-up time ADC reference circuit power-up time Conversion time Sample time Input capacitance Input injection current3, per pin Input injection current, total VREFH current ADCA current ADCB current Quiescent current Calibrated Gain Error (transfer gain) Calibrated Offset Voltage Uncalibrated Gain Error Uncalibrated Offset Voltage Crosstalk between channels Common Mode Voltage Signal-to-noise ratio Signal-to-noise plus distortion ratio Total Harmonic Distortion Spurious Free Dynamic Range Effective Number Of Bits
10% to 90% Input Signal Range 2. ADC clock cycles 3. The current that can be injected or sourced from an unselected ADC signal input without inpacting the performance of the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.
Symbol VADIN RES INL DNL
Min VREFL 12 +/- 1 > -1
Typ -- -- +/- 2.4 +/- 0.7 GUARANTEED
Max VREFH 12 +/- 3.2 < +1
Unit V Bits LSB2 LSB2
fADIC RAD tADPU tVREF tADC tADS CADI IADI IADIT IVREFH IADCA IADCB IADCQ EGAINC VOFFSETC EGAIN VOFFSET
0.5 VREFL 5 -- -- -- -- -- -- -- -- --
-- -- 6 -- 6 1 5 -- -- 1.2 25 25 0
5 VREFH 16 25 -- -- -- 3 20 3 -- -- 10 -- -- 1.01 +/- 30 -- -- -- -- -- -- --
MHz V tAIC cycles2 ms tAIC cycles4 tAIC cycles4 pF mA mA mA mA mA mA -- mV -- mV dB V db db db db bit
-- -- .99 -- --
1 0 .996 to 1.004 +/- 12 -60 (VREFH - VREFLO) / 2 64.6 59.1 60.6 61.1 9.6
Vcommon SNR SINAD THD SFDR ENOB
-- -- -- -- -- --
1. INL measured from Vin = .1VREFH to Vin = .9VREFH
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10.17 Equivalent Circuit for ADC Inputs
Figure 10-23 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to VREFH - VREFH / 2 while the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended analog input is switched to a differential voltage centered about VREFH - VREFH / 2. The switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, VREF and the ADC clock frequency.
Analog Input 3 S1 (VREFH - VREFLO) / 2 1 2 S2 S3 C2 4 C1 S/H C1 = C2 = 1pF
1. 2. 3. 4.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time; 1pf
Figure 10-23 Equivalent Circuit for A/D Loading
10.18 Power Consumption
This section provides additional detail which can be used to optimize power consumption for a given application. Power consumption is given by the following equation: Total power = + + + + A: internal [static component] B: internal [state-dependent component] C: internal [dynamic component] D: external [dynamic component] E: external [static]
A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage current, PLL, and voltage references. These sources operate independently of processor state or operating frequency. B, the internal [state-dependent component], reflects the supply current required by certain on-chip resources only when those resources are in use. These include RAM, Flash memory and the ADCs. C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic.
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Power Consumption
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the IO cell types used on the 56F8346 reveal that the power-versus-load curve does have a non-zero Y-intercept.
Table 10-26 IO Loading Coefficients at 10MHz
Intercept PDU08DGZ_ME PDU04DGZ_ME 2.2 .14 Slope 2.0 .14
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. Table 10-26 provides coefficients for calculating power dissipated in the IO cells as a function of capacitive load. In these cases: TotalPower = ((Intercept +Slope*Cload)*frequency/10MHz) where: * Summation is performed over all output pins with capacitive loads * TotalPower is expressed in mW * Cload is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. The one possible exception to this is if the chip is using the external address and data buses at a rate approaching the maximum system rate. In this case, power from these buses can be significant. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of 8 PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible.
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Part 11 Packaging
11.1 Package and Pin-Out Information 56F8346
This section contains package and pin-out information for the 56F8346. This device comes in a 144-pin low-profile quad flat pack (LQFP). The package outline is shown in Figure 11-1. Figure 11-2 shows the mechanical parameters for the 144-pin LQFP case, and Table 11-1 lists the pin-out for the 144-pin LQFP.
VDD_IO VPP2 CLKO TXD0 RXD0 PHASEA1 PHASEB1 INDEX1 HOME1 A1 A2 A3 A4 A5 VCAP4* VDD_IO A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS D7 D8 D9 VDD_IO D10 GPIOB0 PWMB0 PWMB1 PWMB2
VSS EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VCAP2* CAN_RX CAN_TX VPPI TDO TDI TMS TCK TRST VDD_IO TC0 TD1 TD0 ISA2 ISA1 ISA0 EXTBOOT ANB7 ANB6 ANB5
Orientation Mark Pin 1 109
Motorola 56F8346
37
73
ANB4 ANB3 ANB2 ANB1 ANB0 VSSA_ADC VDDA_ADC VREFH VREFP VREFMID VREFN VREFLO Temp_Sense ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET RSTO VDD_IO VCAP3* EXTAL XTAL VDDA_OSC_PLL OCR_DIS D6 D5 D4 D3 FAULTA2 FAULTA1
* When on-chip regulator is disabled, these four pins are 2.5V VDD_CORE
144
VSS VDD_IO PWMB3 PWMB4 PWMB5 TXD1 RXD1 WR RD PS DS GPIOD0 GPIOD1 ISB0 VCAP1* ISB1 ISB2 IRQA IRQB FAULTB0 FAULTB1 FAULTB2 D0 D1 FAULTB3 PWMA0 VSS PWMA1 PWMA2 VDD_IO PWMA3 PWMA4 VSS PWMA5 FAULTA0 D2
Figure 11-1 Top View, 56F8346 144-Pin LQFP Package
56F8346 Technical Data Preliminary
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Package and Pin-Out Information 56F8346
Table 11-1 56F8346 144-Pin LQFP Package Identification by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Signal Name VDD_IO VPP2 CLKO TXD0 RXD0 PHASEA1 PHASEB1 INDEX1 HOME1 A1 A2 A3 A4 A5 VCAP4 VDD_IO A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS D7 D8 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Signal Name VSS VDD_IO PWMB3 PWMB4 PWMB5 TXD1 RXD1 WR RD PS DS GPIOD0 GPIOD1 ISB0 VCAP1 ISB1 ISB2 IRQA IRQB FAULTB0 FAULTB1 FAULTB2 D0 D1 FAULTB3 PWMA0 VSS PWMA1 PWMA2 Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 Signal Name FAULTA1 FAULTA2 D3 D4 D5 D6 OCR_DIS VDDA_OSC_PLL XTAL EXTAL VCAP3 VDD_IO RSTO RESET CLKMODE ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 Temp_Sense VREFLO VREFN VREFMID VREFP VREFH Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 Signal Name ANB5 ANB6 ANB7 EXTBOOT ISA0 ISA1 ISA2 TD0 TD1 TC0 VDD_IO TRST TCK TMS TDI TDO VPP1 CAN_TX CAN_RX VCAP2 SS0 SCLK0 MISO0 MOSI0 D11 D12 D13 D14 D15
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Table 11-1 56F8346 144-Pin LQFP Package Identification by Pin Number
Pin No. 30 31 32 33 34 35 36 Signal Name D9 VDD_IO D10 GPIOB0 PWMB0 PWMB1 PWMB2 Pin No. 66 67 68 69 70 71 72 Signal Name VDD_IO PWMA3 PWMA4 VSS PWMA5 FAULTA0 D2 Pin No. 102 103 104 105 106 107 108 Signal Name VDDA_ADC VSSA_ADC ANB0 ANB1 ANB2 ANB3 ANB4 Pin No. 138 139 140 141 142 143 144 Signal Name A0 PHASEA0 PHASEB0 INDEX0 HOME0 EMI_MODE VSS
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Package and Pin-Out Information 56F8346
4X
0.20 H B-C D
4X 36 TIPS
0.20 A B-C D
IN 1 NDEX 1
144
109
108
A E1 4 5 E E1/2 VIEW A
36 73
4X
e/2
A C L 7
140X
B
C
3 X X=B, C or D e
E/2
VIEW A
37
72
D D1/2 D/2 D1 D 7 TOP VIEW VIEW B H A
8X NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS B, C AND D TO BE DETERMINED AT DATUM H. 4. THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE SIZE BY A MAXIMUM OF 0.1 mm. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSIONS. THE MAXIMUM ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. PROTRUSIONS SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.35. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD SHALL BE 0.07 mm. 7. DIMENSIONS D AND E TO BE DETERMINED AT THE SEATING PLANE, DATUM A. MILLIMETERS MIN MAX --1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.17 0.23 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 0.50 BSC 22.00 BSC 20.00 BSC 0.45 0.75 1.00 REF 0.50 REF 0.13 0.20 0.13 --0.25 REF 0 7 0 --12 REF
4
5
2
0.1 A
144X
SEATING PLANE
SIDE VIEW
A
PLATING
c
b1
c1
A2
0.05
1 6
BASE METAL
R2 R1
b
0.25
GAGE PLANE
0.08
M
A B-C D
SECTION A-A (ROTATED 90 )
144 PLACES
L2 A1 S L1 VIEW B L
DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 L2 R1 R2 S 1 2
CASE 918-03 ISSUE D DATE 08/22/00
Figure 11-2 56F8346 144-pin LQFP Mechanical Information
MOTOROLA 56F8346 Technical Data Preliminary 147
Part 12 Design Considerations
12.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJ x PD) where: TA = Ambient temperature for the package (oC) RJ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single-layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJ = RJ + RC where: RJA RJC RCA = Package junction-to-ambient thermal resistance C/W = Package junction-to-case thermal resistance C/W = Package case-to-ambient thermal resistance C/W
R JC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, R CA . For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT JT PD
148
= = =
Thermocouple temperature on top of package (oC) Thermal characterization parameter (oC)/W Power dissipation in package (W)
56F8346 Technical Data Preliminary MOTOROLA
Electrical Design Considerations
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
12.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct device operation: * * Provide a low-impedance path from the board power supply to each VDD pin on the device, and from the board ground to each VSS (GND) pin The minimum bypass requirement is to place six 0.01-0.1F capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better performance tolerances. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS Bypass the VDD and VSS layers of the PCB with approximately 100 F, preferably with a high-grade capacitor such as a tantalum capacitor Because the 56F8346's output signals have fast rise and fall times, PCB trace lengths should be minimal Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits.
* * * * *
MOTOROLA
56F8346 Technical Data Preliminary
149
* *
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins Designs that utilize the TRST pin for JTAG port or EOnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together. Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an interface to this port to allow in-circuit Flash programming
*
12.3 Power Distribution and I/O Ring Implementation
Figure 12-1 illustrates the general power control incorporated in the 56F8346. This chip contains an internal regulator which cannot be disabled The regulator takes regulated 3.3V power from the VDD_IO pins and provides 2.5V to the internal logic of the chip. This means the entire part is powered from the 3.3V supply. Notes: * * * Flash, RAM and internal logic are powered from the core regulator output VPP1 and VPP2 are not connected in the customer system All circuitry, analog and digital, share a common VSS bus
VDD VCAP I/O CORE ROSC VSS VSSA_ADC ADC VDDA_ADC VREFH VREFP VREFMID VREFN VREFLO
VDDA_OSC_PLL
OCS
REG
REG
Figure 12-1 56F8346 Power Management
150
56F8346 Technical Data Preliminary
MOTOROLA
Power Distribution and I/O Ring Implementation
Part 13 Ordering Information
Table 13-1 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts.
Table 13-1 56F8346 Ordering Information
Part
MC56F8346
Supply Voltage
3.0-3.6 V
Package Type
Pin Count
144
Frequency (MHz)
60
Temperature Range
-40 to + 105 C
Order Number
MC56F8346VFV60
Low-Profile Quad Flat Pack (LQFP) Low-Profile Quad Flat Pack (LQFP)
MC56F8346
3.0-3.6 V
144
60
-40 to + 125 C
MC56F8346MFV60
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HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T. Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. This product incorporates SuperFlash(R) technology licensed from SST. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2003
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